PADS

Introduction

PADS (formerly PowerPCB) is a PCB design tool originally developed by Innoveda and later acquired by Mentor Graphics (now Siemens EDA). The PADS ASCII export format is a text-based representation of the board and schematic design.

KiCad supports both schematic and PCB layout import.

Supported file types:

  • .asc — PADS ASCII format (PCB and schematic)

  • .txt — Alternative extension (schematic)

LTspice schematics also use the .asc extension. The PCB importer distinguishes PADS files by checking for the !PADS- header prefix on the first line. The schematic importer checks for the *PADS-POWERLOGIC or *PADS-LOGIC header prefix.

File Structure

PADS ASCII files are section-based text files. Each major section is delimited by SECTION markers.

File Header

The first line of a PADS ASCII file is a header that identifies the product, version, and unit system.

!PADS-POWERPCB-V9.4-MILS!              (1)
!PADS-LAYOUT-V2024.2-MM!               (2)
*PADS-LIBRARY-PCB-DECALS-V9*           (3)
*PADS-LOGIC-V9.0*                      (4)
*PADS-POWERLOGIC-V3.0*                 (5)
1 Standard board file with mils as the base unit.
2 Newer PADS Layout product with millimeter units.
3 Library file variant.
4 PADS Logic schematic file.
5 Older PowerLogic schematic file variant.

The header format is !PADS-product-version-units[-mode][-encoding]! where:

Field Values

Product

POWERPCB, PADS, LAYOUT, PADS-LAYOUT

Units

MILS, MM, INCH, BASIC

Mode

Optional. BASIC indicates an alternative unit system.

Encoding

Optional. Character encoding identifier.

Sections

All major sections are marked with SECTION delimiters.

Section Purpose

PCB

Board setup, design rules, thermal parameters, units

PART

Component placements with decals, rotation, attributes

NET

Electrical connectivity (net to pin mapping)

ROUTE

Traces, vias, and routed signals

VIA

Via definitions with drill and size specifications

POUR

Copper pours and zones with priority and fill style

TEXT

Text annotations on the board

BOARD

Board outline geometry

LINES

Graphics, copper shapes, dimension lines

PARTDECAL

Footprint definitions with terminals and pad stacks

PARTTYPE

Component type definitions and attribute templates

REUSE

Reusable hierarchical blocks

CLUSTER

Grouped routes for organized routing

JUMPER

Jumper and bridge definitions

TESTPOINT

Test probe point definitions

NETCLASS

Net class definitions with routing constraints

DIFFPAIR

Differential pair specifications

LAYER

Layer definitions and naming

MISC

Miscellaneous settings

Comment Handling

Lines starting with REMARK are treated as comments and skipped during parsing.

Coordinate System and Units

PADS ASCII files declare their measurement unit in the file header.

Unit String Conversion Factor to Nanometers

MILS

25,400 nm/mil

MM

1,000,000 nm/mm

INCH

25,400,000 nm/inch

BASIC

~0.6667 nm/unit (25,400/38,100)

PADS uses a standard Cartesian coordinate system with Y increasing upward. KiCad uses Y increasing downward, so all Y coordinates are negated during import.

KiCad_x =  pads_x  (converted from file units to nanometers)
KiCad_y = -pads_y

Origin Handling

The board origin is extracted from PCB parameters or computed from the board outline geometry. If a board outline is present, coordinates are adjusted relative to the outline center.

Local Unit Overrides

Parts and decals can specify local units (M = mils, MM = metric, I = inches) that temporarily override the file’s default unit system for the duration of that definition.

Part and Decal Definitions

Part Types (PARTTYPE)

Component type definitions bind a logical component name to one or more decals (footprints) and provide attribute templates.

Part Decals (PARTDECAL)

Footprint definitions containing terminal positions, pad stack geometry, and graphical elements. A part decal defines the physical footprint that is instantiated on the board.

Alternate decals are supported through colon-separated lists with index selection. The importer resolves the primary decal first and falls back to the first available alternative if the primary is missing.

Component Placement (PART)

Each part entry specifies:

  • Component reference designator

  • Decal (footprint) name

  • Board position and rotation

  • Top or bottom layer placement

  • Attributes (value, part type, etc.)

Bottom-layer components are flipped with proper orientation handling.

Shortcut Pattern Expansion

PADS supports shortcut patterns for part and pin naming. For example, C{2-20} expands to C2 through C20. Net pin patterns like U{4-8}.{7-8} create multiple pin combinations. The importer expands these patterns up to a maximum of 10,000 items.

Pad Stack Support

Pad definitions support multiple shapes per layer with separate drill specifications.

Pad Shape Codes

Code Shape KiCad Mapping

R, C, A

Circle

PAD_SHAPE::CIRCLE

S

Square / Rectangle

PAD_SHAPE::RECTANGLE

O

Oval / Obround

PAD_SHAPE::OVAL

RF

Rectangle with finger offset

PAD_SHAPE::RECTANGLE with offset

OF

Oval with finger offset

PAD_SHAPE::OVAL with offset

RC

Rounded corner rectangle

PAD_SHAPE::ROUNDRECT

RT, ST

Thermal shapes

Thermal pad with spoke parameters

Drill Specifications

Each pad stack can specify:

  • Plated vs non-plated drill holes

  • Slotted holes with orientation, length, and offset

  • Per-layer pad dimensions

Tracks, Vias, and Routing

Tracks (ROUTE)

Track segments are organized by signal (net). Each segment specifies a layer, width, and coordinate path. Arc segments within tracks are supported with center point and delta angle.

Via Definitions (VIA)

Named via definitions specify drill diameter and pad sizes. The importer supports through-hole, blind, buried, and microvias based on the start and end layer specifications.

Clusters (CLUSTER)

Grouped route segments for organizational purposes. These are imported as PCB_GROUP objects in KiCad.

Copper Zones (POUR)

Copper pour definitions include outline geometry, net assignment, fill style, and priority.

Priority Handling

PADS uses lower numbers for higher priority while KiCad uses higher numbers for higher priority. The importer converts priorities accordingly.

kicadPriority = maxPriority - padsPriority + 1

Thermal Relief

Per-pour thermal parameters are supported, with fallback to global defaults from the board setup. These are applied to zone-to-pad connections as spoke width and gap.

Design Rules

The importer extracts board-level design rules from the PCB section and applies them to the KiCad board design settings.

PADS Rule KiCad Setting

Minimum Clearance

m_MinClearance

Default Clearance

Default netclass and zone clearance

Minimum Track Width

m_TrackMinWidth

Default Track Width

Custom track width

Minimum Via Size

m_ViasMinSize

Default Via Size

Custom via size

Minimum Via Drill

m_MinThroughDrill

Default Via Drill

Custom via drill

Hole-to-Hole Spacing

m_HoleToHoleMin

Silk Clearance

m_SilkClearance

Solder Mask Clearance

m_SolderMaskExpansion

Net Classes (NETCLASS)

Named net class definitions with routing constraints are imported as KiCad netclasses.

Differential Pairs (DIFFPAIR)

Named differential pair definitions with positive/negative net assignments, gap, and width specifications. These are converted to DRC rules written to a .kicad_dru file alongside the imported board.

Reuse Blocks (REUSE)

Hierarchical circuit blocks that can be instantiated multiple times. Each reuse block defines part naming schemes (prefix, suffix) and net naming schemes (with merge options).

Reuse blocks are imported as PCB_GROUP objects. Parts within a reuse block are associated via an internal PADS_Reuse_Block field.

Layer Mapping

Copper Layers

PADS copper layer numbering:

  • Layer 1: Top copper

  • Layer 2 to N-1: Inner copper layers

  • Layer N: Bottom copper (where N = total layer count)

In pad stack definitions, negative layer numbers have special meaning: -2 = top, -1 = bottom, 0 = all layers.

Non-Copper Layer Mapping

The layer mapper recognizes layer names (case-insensitive) and maps them to KiCad layers.

PADS Layer Pattern KiCad Layer

Silkscreen Top, Silk Top, SST, Top Overlay

F.SilkS

Silkscreen Bottom, Silk Bottom, SSB

B.SilkS

Solder Mask Top, SMT

F.Mask

Solder Mask Bottom, SMB

B.Mask

Paste Top

F.Paste

Paste Bottom

B.Paste

Assembly Top

F.Fab

Assembly Bottom

B.Fab

Board Outline

Edge.Cuts

Non-copper layers also have default numeric mappings:

Number KiCad Layer

21

F.Fab (Assembly Top)

22

B.Fab (Assembly Bottom)

25

F.Mask (Solder Mask Top)

26

F.SilkS (Silkscreen Top)

27

B.SilkS (Silkscreen Bottom)

28

B.Mask (Solder Mask Bottom)

29

F.Paste (Paste Top)

30

B.Paste (Paste Bottom)

Unmapped layers generate warnings and are assigned to the Comments layer.

Board Outline (BOARD)

The board outline section defines the board edge geometry. Arc segments within the outline are supported. The outline is mapped to the Edge.Cuts layer.

Text (TEXT)

Text annotations with full formatting support including character height and width scaling, justification, mirroring, and font information. Text scaling factors are configurable via ADVANCED_CONFIG settings.

The PADS text anchor differs from KiCad’s anchor by a small offset. The importer compensates for this via a configurable offset parameter.

Schematic Format (PADS-LOGIC / PADS-POWERLOGIC)

The schematic importer handles PADS Logic ASCII export files. These files use SECTION delimiters similar to the PCB format but contain schematic-specific data.

Schematic Sections

Section Purpose

SCH

Schematic parameters (grid, fonts, text sizes, wire/bus widths)

FIELDS

User-defined fields and title block data

SHT

Sheet headers with sheet names and hierarchy

CAEDECAL

Symbol definitions with graphic primitives and pin layouts

PARTTYPE

Part type definitions binding components to symbol variants

PART

Component placements with position, rotation, gate index, attributes

CONNECTION

Signal definitions with wire segments and pin connectivity

OFFPAGE REFS

Off-page connectors (power symbols and inter-sheet references)

TIEDOTS

Junction dot positions

TEXT

Free text annotations

LINES

Graphic lines, circles, rectangles, and arcs

NETNAMES

Net name label positions and formatting

Multi-Sheet Support

The importer supports multi-sheet designs. When multiple sheet numbers are detected in the part placements and signal data, the importer creates hierarchical sub-sheets under the root sheet. Each sub-sheet receives a page number and optional name from the SHT section headers.

Symbol Definitions (CAEDECAL)

Symbol definitions contain graphic primitives (lines, rectangles, circles, arcs) and pin definitions. Each pin specifies position, type, length, rotation, and optional inverted or clock decorators.

Part Types and Gates (PARTTYPE)

Part type definitions can contain multiple gates, each with its own symbol variant. Multi-gate components (e.g., a quad NAND gate) are imported as multi-unit KiCad symbols. The gate separator character (dash or dot, e.g., U17-A) is auto-detected and applied to the schematic settings.

Special keywords ($GND_SYMS, $PWR_SYMS, $OSR_SYMS) identify power and ground symbols. These are mapped to KiCad standard power library symbols where a matching style exists.

Schematic Coordinate System

PADS Logic uses Y increasing upward. The importer converts to KiCad’s Y-down coordinate system using the page height.

KiCad_x = pads_x  (converted from mils to KiCad internal units)
KiCad_y = pageHeight - pads_y

Schematic Imported Elements

  • Symbols with reference designator, value, and custom attribute fields

  • Multi-unit symbols from multi-gate part types

  • Pin types (passive, input, output, bidirectional, tristate, open collector, open emitter, power)

  • Wire segments and connectivity

  • Junction dots from TIEDOTS

  • Net labels at dangling wire endpoints

  • Global labels from off-page connectors

  • Power and ground symbols mapped to KiCad standard power library (VCC, GND, etc.)

  • Power symbol orientation derived from connected wire direction

  • Text annotations with height, width, justification, and rotation

  • Graphic primitives (lines, rectangles, circles, arcs) with fill and line style

  • Multi-sheet hierarchical structure with named sub-sheets

  • Title block from FIELDS section

  • Deterministic UUIDs for PCB cross-probe linking

  • Passive component value override from VALUE1 parametric attribute

PCB Imported Elements

  • Footprints with reference designator, value, and attribute fields, with position, rotation, and top/bottom layer placement

  • Pads with shapes (circle, rectangle, oval, rounded rectangle, thermal) including drill definitions with plated/unplated distinction, slotted holes, per-layer dimensions, and finger pad support

  • Tracks and arcs on copper layers with width and net assignment

  • Vias with through-hole, blind, buried, and microvia type support

  • Nets and net classes with routing constraints

  • Differential pair definitions converted to DRC rules

  • Copper zones with priority handling, thermal relief parameters, and net assignment

  • Keepout areas (routing, via, copper, and placement keepouts)

  • Board outline with arc support mapped to Edge.Cuts

  • Text annotations with font properties and scaling

  • Dimension lines

  • Graphic lines and circles

  • Reuse blocks imported as PCB_GROUP objects

  • Clusters (grouped routes) imported as PCB_GROUP objects

  • Test point definitions

  • Design rules (clearances, track widths, via sizes, hole spacing, mask expansions)

Limitations

  • Footprint library browsing is not supported; PADS files are board-import and schematic-import only.

  • Through-hole vias can duplicate across multiple SIGNAL blocks for the same net. The importer deduplicates by position.

  • Unmapped layers are assigned to the Comments layer with a warning.

  • Copper-layer attributes on decals are redirected to the corresponding silkscreen layer.

  • PADS text anchoring differs from KiCad’s by a small offset that is compensated via configurable parameters in ADVANCED_CONFIG.

  • Footprint lookup falls back to the first available alternate decal if the primary decal is missing, with a warning.

  • The format does not carry schematic cross-reference data, so deterministic UUID generation is used for cross-probe linking.