CADSTAR

Introduction

CADSTAR is a PCB design suite from Zuken. KiCad imports CADSTAR Schematic Archive, PCB Archive, and Parts Library files. Schematic and PCB files are imported separately; there is no project-level import.

Supported file types:

.csa — CADSTAR Schematic Archive
.cpa — CADSTAR PCB Archive (also serves as a footprint library source)
.lib — CADSTAR Parts Library

Both archive formats use an S-expression-like structure parsed into an XNODE tree. The Parts Library uses a separate text-based format parsed with a PEGTL PEG grammar.

Archive File Structure

CADSTAR archive files (.csa and .cpa) use a parenthesized token format similar to S-expressions, encoded as Windows-1252 text. DSNLEXER parses them into an XNODE tree. Each node name is the first token after an opening parenthesis; subsequent tokens become numbered XML-style attributes (attr0, attr1, etc.).

File Identification

The outermost node identifies the file type:

CADSTARSCM — Schematic Archive
CADSTARPCB — PCB Archive (also used when FORMAT type is LIBRARY)

(CADSTARPCB
  (HEADER ...)
  (ASSIGNMENTS ...)
  (LIBRARY ...)
  (DEFAULTS ...)
  (PARTS ...)
  (LAYOUT ...)
  (DISPLAY ...)
)

(CADSTARSCM
  (HEADER ...)
  (ASSIGNMENTS ...)
  (LIBRARY ...)
  (DEFAULTS ...)
  (PARTS ...)
  (SHEETS ...)
  (SCHEMATIC ...)
  (DISPLAY ...)
)

HEADER

The HEADER node contains file metadata.

(HEADER
  (FORMAT "LAYOUT" 0 21)
  (JOBFILE "design.pcb")
  (JOBTITLE "My Design")
  (GENERATOR "CADSTAR 2020.0")
  (RESOLUTION
    (METRIC "HUNDREDTH" "MICRON")
  )
  (TIMESTAMP 2020 3 15 10 30 0)
)

Child Node Description

Child Node	Description
`FORMAT`	`attr0`=type (`LAYOUT` or `LIBRARY` for PCB, schematic type for CSA), `attr1`=unknown integer, `attr2`=version number
`JOBFILE`	Original design filename
`JOBTITLE`	Design title string
`GENERATOR`	Application that created the archive
`RESOLUTION`	Contains `METRIC` child, only known value is `HUNDREDTH MICRON`
`TIMESTAMP`	Six integer attributes: year, month, day, hour, minute, second

FORMAT

attr0=type (LAYOUT or LIBRARY for PCB, schematic type for CSA), attr1=unknown integer, attr2=version number

JOBFILE

Original design filename

JOBTITLE

Design title string

GENERATOR

Application that created the archive

RESOLUTION

Contains METRIC child, only known value is HUNDREDTH MICRON

TIMESTAMP

Six integer attributes: year, month, day, hour, minute, second

Version Compatibility

The FORMAT node attr2 field contains the archive version number.

Version	CADSTAR Release
8	CADSTAR v6
9	CADSTAR v7+
19	CADSTAR 17.0
20	CADSTAR 18.0
21	CADSTAR 2018.0 / 2019.0 / 2020.0

CADSTAR v6 (version 8) files store angles in 1/10 degree units. Version 9 and later files use 1/1000 degree units.

Unit System

All coordinate and dimension values in the archive are stored in hundredths of a micron. The RESOLUTION node always declares METRIC HUNDREDTH MICRON. The conversion to KiCad internal units multiplies by PCB_IU_PER_MM / 1e5 (PCB) or SCH_IU_PER_MM / 1e5 (schematic).

Angles throughout the format are in 1/1000 of a degree unless the file version is 8 (CADSTAR v6), where angles are in 1/10 of a degree.

Common Geometry Types

Several primitive types appear throughout both archive formats:

Node Structure

Node	Structure
`PT`	Point with `attr0`=x, `attr1`=y in hundredth-micron coordinates
`E`	Engineering value with `attr0`=base, `attr1`=exponent; value = base * 10^exponent
`CWARC`	Clockwise arc; two child `PT` nodes (center, endpoint)
`ACWARC`	Anticlockwise arc; two child `PT` nodes (center, endpoint)
`CWSEMI`	Clockwise semicircle; one child `PT` node (endpoint)
`ACWSEMI`	Anticlockwise semicircle; one child `PT` node (endpoint)

PT

Point with attr0=x, attr1=y in hundredth-micron coordinates

E

Engineering value with attr0=base, attr1=exponent; value = base * 10^exponent

CWARC

Clockwise arc; two child PT nodes (center, endpoint)

ACWARC

Anticlockwise arc; two child PT nodes (center, endpoint)

CWSEMI

Clockwise semicircle; one child PT node (endpoint)

ACWSEMI

Anticlockwise semicircle; one child PT node (endpoint)

Shapes are built from sequences of these vertex nodes and appear in one of four container types:

Shape Node Description

Shape Node	Description
`OPENSHAPE`	Open polyline, no fill, no cutouts
`OUTLINE`	Closed unfilled polygon
`SOLID`	Closed polygon with solid fill
`HATCHED`	Closed polygon with hatch fill; `attr0`=HATCHCODE_ID

OPENSHAPE

Open polyline, no fill, no cutouts

OUTLINE

Closed unfilled polygon

SOLID

Closed polygon with solid fill

HATCHED

Closed polygon with hatch fill; attr0=HATCHCODE_ID

Each shape contains an ordered sequence of vertex child nodes. A CUTOUT child within a closed shape defines an interior hole as another vertex sequence.

CODEDEFS (Common)

The CODEDEFS node appears within ASSIGNMENTS and defines style codes shared between schematic and PCB archives.

Child Node Description

Child Node	Description
`LINECODE`	Line style: `attr0`=ID, `attr1`=name, `attr2`=width. Child `STYLE` with value `SOLID`, `DASH`, `DASHDOT`, `DASHDOTDOT`, or `DOT`
`HATCHCODE`	Hatch pattern: `attr0`=ID, `attr1`=name. Contains one or more `HATCH` children
`TEXTCODE`	Text style: `attr0`=ID, `attr1`=name, `attr2`=line width, `attr3`=height, `attr4`=width. Optional `FONT` child
`ROUTECODE`	Route width: `attr0`=ID, `attr1`=name. Children: `SROUTEWIDTH`, `MINWIDTH`, `MAXWIDTH`, `NECKWIDTH`, `ROUTEREASSIGN`
`ATTRNAME`	Attribute definition: `attr0`=ID, `attr1`=name. Internal attributes have names in parentheses such as `(PartDescription)`
`NETCLASS`	Net class: `attr0`=ID, `attr1`=name
`SPCCLASSNAME`	Spacing class: `attr0`=ID, `attr1`=name

LINECODE

Line style: attr0=ID, attr1=name, attr2=width. Child STYLE with value SOLID, DASH, DASHDOT, DASHDOTDOT, or DOT

HATCHCODE

Hatch pattern: attr0=ID, attr1=name. Contains one or more HATCH children

TEXTCODE

Text style: attr0=ID, attr1=name, attr2=line width, attr3=height, attr4=width. Optional FONT child

ROUTECODE

Route width: attr0=ID, attr1=name. Children: SROUTEWIDTH, MINWIDTH, MAXWIDTH, NECKWIDTH, ROUTEREASSIGN

ATTRNAME

Attribute definition: attr0=ID, attr1=name. Internal attributes have names in parentheses such as (PartDescription)

NETCLASS

Net class: attr0=ID, attr1=name

SPCCLASSNAME

Spacing class: attr0=ID, attr1=name

Schematic Archive (.csa)

A .csa file has the root node CADSTARSCM and the following top-level structure:

CADSTARSCM
 +-- HEADER
 +-- ASSIGNMENTS
 |    +-- CODEDEFS  (common codes + TERMINALCODE)
 |    +-- GRIDS
 |    +-- SETTINGS  (design origin, area, units)
 +-- LIBRARY
 |    +-- SYMDEF ...  (symbol definitions)
 +-- DEFAULTS
 +-- PARTS
 |    +-- PART ...  (part definitions with pin mappings)
 +-- SHEETS
 |    +-- SHEET ...  (sheet names and ordering)
 +-- SCHEMATIC
 |    +-- GROUP ...
 |    +-- REUSEBLOCK ...
 |    +-- FIGURE ...
 |    +-- SYMBOL ...
 |    +-- BUS ...
 |    +-- BLOCK ...
 |    +-- NET ...
 |    +-- TEXT ...
 |    +-- DOCSYMBOL ...
 |    +-- VHIERARCHY
 +-- DISPLAY
      +-- ATTRCOLORS
      +-- SCMITEMCOLORS

Terminal Codes

Schematic archives extend CODEDEFS with TERMINALCODE entries that define the shape of connection points on symbols.

(TERMINALCODE "TC1" "Standard Pin"
  (ANNULUS 5000 ...)
)

Field Description

Field	Description
`attr0`	TERMINALCODE_ID
`attr1`	Name
Child shape node	One of the terminal shape types (see table below)
`FILLED`	Optional flag indicating the terminal shape is filled

attr0

TERMINALCODE_ID

attr1

Name

Child shape node

One of the terminal shape types (see table below)

FILLED

Optional flag indicating the terminal shape is filled

Terminal Shape Types

Keyword Shape

Keyword	Shape
`ANNULUS`	Ring
`BOX`	Rectangular box
`BULLET`	Bullet
`ROUND`	Circle
`CROSS`	Cross
`DIAMOND`	Diamond
`FINGER`	Elongated finger
`OCTAGON`	Octagon
`PLUS`	Plus sign
`POINTER`	Pointer / arrow
`RECTANGLE`	Rectangle
`ROUNDED`	Rounded rectangle
`SQUARE`	Square
`STAR`	Star
`TRIANGLE`	Triangle

ANNULUS

Ring

BOX

Rectangular box

BULLET

Bullet

ROUND

Circle

CROSS

Cross

DIAMOND

Diamond

FINGER

Elongated finger

OCTAGON

Octagon

PLUS

Plus sign

POINTER

Pointer / arrow

RECTANGLE

Rectangle

ROUNDED

Rounded rectangle

SQUARE

Square

STAR

Star

TRIANGLE

Triangle

Shape parameters follow the shape keyword as attributes: attr0=size, attr1=left length (optional), attr2=right length (optional), attr3=internal feature (optional). An ORIENT child specifies angle.

Symbol Definitions (SYMDEF)

Symbol definitions live in the LIBRARY node. Each SYMDEF defines a reusable schematic symbol.

(SYMDEF "SD1" "RESISTOR" "A"
  (PT 0 0)           ;; Origin
  (TERMINAL 1 "TC1"
    (PT 0 -50000)
    (ORIENT 0)
  )
  (TERMINAL 2 "TC1"
    (PT 0 50000)
    (ORIENT 1800000)
  )
  (FIGURE ...)
  (TEXT ...)
  (TEXTLOC ...)
  (ATTR ...)
)

Field Description

Field	Description
`attr0`	SYMDEF_ID
`attr1`	Reference name (library identifier)
`attr2`	Alternate name (variant within the same base symbol)
`PT` (first)	Component origin point
`VERSION`	Sequential integer for library/design discrepancy detection
`STUB`	Present if the archive was exported without the component library
`TERMINAL`	Pin connection point: `attr0`=TERMINAL_ID (long), `attr1`=TERMINALCODE_ID
`FIGURE`	Graphical shape elements
`TEXT`	Text elements
`TEXTLOC`	Attribute display locations including designator position
`PINNUMLOC`	Pin number label location for a terminal
`PINLABELLOC`	Pin name label location for a terminal

attr0

SYMDEF_ID

attr1

Reference name (library identifier)

attr2

Alternate name (variant within the same base symbol)

PT (first)

Component origin point

VERSION

Sequential integer for library/design discrepancy detection

STUB

Present if the archive was exported without the component library

TERMINAL

Pin connection point: attr0=TERMINAL_ID (long), attr1=TERMINALCODE_ID

FIGURE

Graphical shape elements

TEXT

Text elements

TEXTLOC

Attribute display locations including designator position

PINNUMLOC

Pin number label location for a terminal

PINLABELLOC

Pin name label location for a terminal

Symbols (Instances)

Symbol instances in the SCHEMATIC node reference a SYMDEF and add placement data.

(SYMBOL "S1" "SD1" "LAY1"
  (PT 100000 200000)
  (ORIENT 0)
  (COMP "R1")
  (PARTREF "P1")
  (GATE "A")
  ...
)

Key fields:

Field Description

Field	Description
`attr0`	SYMBOL_ID
`attr1`	SYMDEF_ID reference
`attr2`	LAYER_ID (sheet)
`PT`	Placement origin
`ORIENT`	Orientation angle (1/1000 degree)
`MIRROR`	Present if mirrored
`COMP`	Component reference designator
`PARTREF`	Part library reference ID
`GATE`	Gate identifier within the part
`SYMBOLVARIANT`	Signal reference type: `GLOBALSIGNAL`, `SIGNALREF`, or `TESTPOINT`
`SIGREFLINK`	Cross-reference sheet annotation for signal references
`SCALENUM` / `SCALEDENOM`	Arbitrary symbol scaling as numerator/denominator ratio

attr0

SYMBOL_ID

attr1

SYMDEF_ID reference

attr2

LAYER_ID (sheet)

PT

Placement origin

ORIENT

Orientation angle (1/1000 degree)

MIRROR

Present if mirrored

COMP

Component reference designator

PARTREF

Part library reference ID

GATE

Gate identifier within the part

SYMBOLVARIANT

Signal reference type: GLOBALSIGNAL, SIGNALREF, or TESTPOINT

SIGREFLINK

Cross-reference sheet annotation for signal references

SCALENUM / SCALEDENOM

Arbitrary symbol scaling as numerator/denominator ratio

Nets (Schematic)

Schematic nets contain several element types, each with an ID prefix convention:

Node ID Prefix Description

Node	ID Prefix	Description
`TERM`	`P`	Symbol terminal connection
`JPT`	`J`	Junction point with optional net label
`BUSTERM`	`BT`	Bus terminal connection (point on bus + wire start point)
`BLOCKTERM`	`BLKT`	Block terminal connection (hierarchical)
`DANGLER`	`D`	Dangling wire end
`CONN`	—	Connection (wire) between two net elements

TERM

P

Symbol terminal connection

JPT

J

Junction point with optional net label

BUSTERM

BT

Bus terminal connection (point on bus + wire start point)

BLOCKTERM

BLKT

Block terminal connection (hierarchical)

DANGLER

D

Dangling wire end

CONN

—

Connection (wire) between two net elements

Net properties: SIGNAME (net name), SIGNUM (signal number for unnamed nets), NETCODE (route code reference), NETCLASSREF, SPACINGCLASS.

Connections contain a LayerID (sheet), a sequence of PT nodes defining the wire path, and a LINECODEREF for the wire line style.

Buses

(BUS "B1" "LC1" "LAY1"
  (OPENSHAPE
    (PT 100000 200000)
    (PT 100000 300000)
  )
  (BUSNAME "DATA[0:7]")
  (SIGLOC ...)
)

Blocks

Blocks define hierarchical sheet structure:

Type Description

Type	Description
`CLONE`	References the sheet the block is on
`PARENT`	Parent sheet reference
`CHILD`	Child sheet reference

CLONE

References the sheet the block is on

PARENT

Parent sheet reference

CHILD

Child sheet reference

Each block has an AssocLayerID linking to the associated parent or child sheet, and may contain TERMINAL and FIGURE children for block port connections.

Sheets

The SHEETS node maps LAYER_IDs to sheet names and defines display order:

(SHEETS
  (SHEET "LAY1" "Sheet 1")
  (SHEET "LAY2" "Sheet 2")
  ...
)

PCB Archive (.cpa)

A .cpa file has the root node CADSTARPCB and the following top-level structure:

CADSTARPCB
 +-- HEADER
 +-- ASSIGNMENTS
 |    +-- LAYERDEFS
 |    |    +-- LAYERSTACK
 |    |    +-- MATERIAL ...
 |    |    +-- LAYER ...
 |    |    +-- SWAPPAIR ...
 |    +-- CODEDEFS  (common codes + PADCODE, VIACODE, COPPERCODE, SPACINGCODE, etc.)
 |    +-- TECHNOLOGY  (design rules, grid settings)
 |    +-- GRIDS
 +-- LIBRARY
 |    +-- SYMDEF ...  (component/footprint definitions)
 +-- DEFAULTS
 +-- PARTS
 |    +-- PART ...  (part definitions with pin mappings)
 +-- LAYOUT
 |    +-- GROUP ...
 |    +-- REUSEBLOCK ...
 |    +-- BOARD ...
 |    +-- FIGURE ...
 |    +-- AREA ...
 |    +-- COMPONENT ...
 |    +-- DOCSYMBOL ...
 |    +-- TRUNK ...
 |    +-- NET ...  (tracks, vias, connections)
 |    +-- TEMPLATE ...  (copper pour zones)
 |    +-- COPPER ...  (poured copper shapes)
 |    +-- TEXT ...
 |    +-- DIMENSION ...
 |    +-- DRILLTABLE ...
 |    +-- VHIERARCHY
 +-- DISPLAY

Layer Definitions

The LAYERDEFS node within ASSIGNMENTS defines the PCB stackup.

(LAYERDEFS
  (LAYERSTACK "LAY1" "LAY2" "LAY3" ...)
  (MATERIAL "MAT1" "FR4" "NONELEC"
    (RELPERMIT (E 42 -1))
    (LOSSTANGENT (E 2 -2))
    (RESISTIVITY (E 17 1))
  )
  (LAYER "LAY1" "Top Copper"
    (ELEC 1
      (MAKE "MAT1" 35000)
    )
  )
  (SWAPPAIR "LAY1" "LAY3")
)

Layer Types

Keyword Description

Keyword	Description
`ALLLAYER`	Built-in: all layers
`ALLELEC`	Built-in: all electrical layers
`ALLDOC`	Built-in: all documentation layers
`NOLAYER`	Built-in: no layer
`ASSCOMPCOPP`	Built-in: associated component copper
`JUMPERLAYER`	Built-in: jumper layer
`ELEC`	Electrical copper layer; `attr0`=physical layer number
`POWER`	Power plane layer; `attr0`=physical layer number
`NONELEC`	Non-electrical layer with subtypes
`CONSTRUCTION`	Construction layer
`DOC`	Documentation layer

ALLLAYER

Built-in: all layers

ALLELEC

Built-in: all electrical layers

ALLDOC

Built-in: all documentation layers

NOLAYER

Built-in: no layer

ASSCOMPCOPP

Built-in: associated component copper

JUMPERLAYER

Built-in: jumper layer

ELEC

Electrical copper layer; attr0=physical layer number

POWER

Power plane layer; attr0=physical layer number

NONELEC

Non-electrical layer with subtypes

CONSTRUCTION

Construction layer

DOC

Documentation layer

Layer Subtypes (NONELEC)

Keyword Subtype

Keyword	Subtype
`LAYERSUBTYPE_SILKSCREEN`	Silkscreen
`LAYERSUBTYPE_PLACEMENT`	Placement
`LAYERSUBTYPE_ASSEMBLY`	Assembly
`LAYERSUBTYPE_SOLDERRESIST`	Solder resist
`LAYERSUBTYPE_PASTE`	Solder paste
`LAYERSUBTYPE_CLEARANCE`	Clearance
`LAYERSUBTYPE_ROUT`	Board routing/outline

LAYERSUBTYPE_SILKSCREEN

Silkscreen

LAYERSUBTYPE_PLACEMENT

Placement

LAYERSUBTYPE_ASSEMBLY

Assembly

LAYERSUBTYPE_SOLDERRESIST

Solder resist

LAYERSUBTYPE_PASTE

Solder paste

LAYERSUBTYPE_CLEARANCE

Clearance

LAYERSUBTYPE_ROUT

Board routing/outline

Layer Properties

Each LAYER node can contain:

Child Node Description

Child Node	Description
`MAKE`	`attr0`=MATERIAL_ID, `attr1`=thickness. Optional `EMBEDS` child (`UPWARDS` or `DOWNWARDS`)
`LAYERHEIGHT`	`attr0`=thickness (alternative to MAKE for layers without material)
`BIAS`	Routing bias: `UNBIASED`, `X_BIASED`, `Y_BIASED`, `ANTITRACK`, `OBSTACLE`
`REFPLANE`	Present if this layer is a reference plane
`VARIANTLAYER`	Present if this is a variant layer

MAKE

attr0=MATERIAL_ID, attr1=thickness. Optional EMBEDS child (UPWARDS or DOWNWARDS)

LAYERHEIGHT

attr0=thickness (alternative to MAKE for layers without material)

BIAS

Routing bias: UNBIASED, X_BIASED, Y_BIASED, ANTITRACK, OBSTACLE

REFPLANE

Present if this layer is a reference plane

VARIANTLAYER

Present if this is a variant layer

Material Properties

Child Node Description

Child Node	Description
`RELPERMIT`	Relative permittivity (dielectric constant), contains `E` value
`LOSSTANGENT`	Dielectric loss tangent, contains `E` value
`RESISTIVITY`	Resistivity in units of 10^-8 ohm-metre, contains `E` value

RELPERMIT

Relative permittivity (dielectric constant), contains E value

LOSSTANGENT

Dielectric loss tangent, contains E value

RESISTIVITY

Resistivity in units of 10^-8 ohm-metre, contains E value

Material types: CONSTRUCTION, ELECTRICAL, NONELEC.

PCB Code Definitions

The PCB CODEDEFS node extends the common codes with additional PCB-specific entries:

Child Node Description

Child Node	Description
`COPPERCODE`	Copper fill width: `attr0`=ID, `attr1`=name, `attr2`=width. Contains optional `COPREASSIGN` per-layer overrides
`SPACINGCODE`	Spacing design rule: `attr0`=ID, `attr1`=spacing value. Contains optional `REASSIGN` per-layer overrides
`PADCODE`	Pad definition (see below)
`VIACODE`	Via definition (see below)
`LAYERPAIR`	Default via between layer pair: `attr0`=ID, `attr1`=name, physical layer start/end, VIACODE_ID reference
`RULESET`	Area-specific design rule set: `attr0`=ID, `attr1`=name. Children: `ROUCODEREF`, `VIACODEREF`, `SPACINGCODE`
`SPCCLASSSPACE`	Spacing class pair rule: two SPACING_CLASS_IDs, LAYER_ID, spacing value

COPPERCODE

Copper fill width: attr0=ID, attr1=name, attr2=width. Contains optional COPREASSIGN per-layer overrides

SPACINGCODE

Spacing design rule: attr0=ID, attr1=spacing value. Contains optional REASSIGN per-layer overrides

PADCODE

Pad definition (see below)

VIACODE

Via definition (see below)

LAYERPAIR

Default via between layer pair: attr0=ID, attr1=name, physical layer start/end, VIACODE_ID reference

RULESET

Area-specific design rule set: attr0=ID, attr1=name. Children: ROUCODEREF, VIACODEREF, SPACINGCODE

SPCCLASSSPACE

Spacing class pair rule: two SPACING_CLASS_IDs, LAYER_ID, spacing value

Pad Codes

(PADCODE "PC1" "SMD_1206"
  (RECTANGLE 120000 30000 30000)
  (RELIEFWIDTH 25000)
  (RELIEFCLEARANCE 20000)
  (DRILL 0)
)

Field Description

Field	Description
`attr0`	PADCODE_ID
`attr1`	Name
Shape node	Pad shape (see pad shape table below)
`RELIEFCLEARANCE`	Thermal relief clearance
`RELIEFWIDTH`	Thermal relief spoke width
`DRILL`	Drill diameter; `attr0`=diameter
`DRILLOVERSIZE`	Drill oversize
`SLOTLENGTH`	Slot length for oblong drills
`SLOTORIENT`	Slot orientation angle
`DRILLXOFFSET`	X offset of drill from pad center
`DRILLYOFFSET`	Y offset of drill from pad center
`PLATED`	Present if through-hole pad is plated (default true)
`PADREASSIGN`	Per-layer shape override: LAYER_ID + shape node

attr0

PADCODE_ID

attr1

Name

Shape node

Pad shape (see pad shape table below)

RELIEFCLEARANCE

Thermal relief clearance

RELIEFWIDTH

Thermal relief spoke width

DRILL

Drill diameter; attr0=diameter

DRILLOVERSIZE

Drill oversize

SLOTLENGTH

Slot length for oblong drills

SLOTORIENT

Slot orientation angle

DRILLXOFFSET

X offset of drill from pad center

DRILLYOFFSET

Y offset of drill from pad center

PLATED

Present if through-hole pad is plated (default true)

PADREASSIGN

Per-layer shape override: LAYER_ID + shape node

Pad Shape Types

Keyword Enum Value Shape Parameters

Keyword	Enum Value	Shape Parameters
`ANNULUS`	ANNULUS	`attr0`=outer size, `attr1`=internal feature
`BULLET`	BULLET	`attr0`=size, `attr1`=left length, `attr2`=right length
`ROUND`	CIRCLE	`attr0`=diameter
`DIAMOND`	DIAMOND	`attr0`=size
`FINGER`	FINGER	`attr0`=size, `attr1`=left length, `attr2`=right length
`OCTAGON`	OCTAGON	`attr0`=size
`RECTANGLE`	RECTANGLE	`attr0`=size, `attr1`=left length, `attr2`=right length
`ROUNDED`	ROUNDED_RECT	`attr0`=size, `attr1`=left length, `attr2`=right length, `attr3`=internal feature
`SQUARE`	SQUARE	`attr0`=size

ANNULUS

ANNULUS

attr0=outer size, attr1=internal feature

BULLET

BULLET

attr0=size, attr1=left length, attr2=right length

ROUND

CIRCLE

attr0=diameter

DIAMOND

DIAMOND

attr0=size

FINGER

FINGER

attr0=size, attr1=left length, attr2=right length

OCTAGON

OCTAGON

attr0=size

RECTANGLE

RECTANGLE

attr0=size, attr1=left length, attr2=right length

ROUNDED

ROUNDED_RECT

attr0=size, attr1=left length, attr2=right length, attr3=internal feature

SQUARE

SQUARE

attr0=size

All pad shapes may have an ORIENT child node specifying rotation in 1/1000 degree.

Via Codes

(VIACODE "VC1" "Standard Via"
  (ROUND 60000)
  (DRILL 30000)
  (RELIEFCLEARANCE 20000)
  (RELIEFWIDTH 25000)
)

Via codes have the same structure as pad codes but without slot-related fields. Per-layer overrides use VIAREASSIGN nodes.

Spacing Code Rules

The spacing code ID encodes the rule type. Known spacing rule identifiers:

ID Rule

ID	Rule
`A_A`	Component placement to component placement
`C_B`	Copper to board outline
`C_C`	Copper to copper
`H_H`	Hole to hole
`P_B`	Pad to board
`P_C`	Pad to copper
`P_P`	Pad to pad
`P_S`	Pad to SMD pad (optional)
`P_V`	Pad to via
`T_B`	Route to board outline
`T_C`	Route to copper
`T_P`	Route to pad
`T_T`	Route to route
`T_S`	Route to SMD pad (optional)
`T_V`	Route to via
`V_B`	Via to board
`V_C`	Via to copper
`V_S`	Via to SMD pad (optional)
`V_V`	Via to via
`S_B`	SMD pad to board (optional)
`S_C`	SMD pad to copper (optional)
`S_S`	SMD pad to SMD pad (optional)
`L_B`	Test land to board
`L_O`	Test land to component
`L_L`	Test land to test land
`OT_P`	Optimal route to pad (optional)
`OT_T`	Optimal route to route (optional)
`OT_V`	Optimal route to via (optional)

A_A

Component placement to component placement

C_B

Copper to board outline

C_C

Copper to copper

H_H

Hole to hole

P_B

Pad to board

P_C

Pad to copper

P_P

Pad to pad

P_S

Pad to SMD pad (optional)

P_V

Pad to via

T_B

Route to board outline

T_C

Route to copper

T_P

Route to pad

T_T

Route to route

T_S

Route to SMD pad (optional)

T_V

Route to via

V_B

Via to board

V_C

Via to copper

V_S

Via to SMD pad (optional)

V_V

Via to via

S_B

SMD pad to board (optional)

S_C

SMD pad to copper (optional)

S_S

SMD pad to SMD pad (optional)

L_B

Test land to board

L_O

Test land to component

L_L

Test land to test land

OT_P

Optimal route to pad (optional)

OT_T

Optimal route to route (optional)

OT_V

Optimal route to via (optional)

Additional design rules in the TECHNOLOGY node: MAXMITER, MINMITER, MINUNNECKED, MINNECKED, MINROUTEWIDTH.

TECHNOLOGY Section

The TECHNOLOGY node extends SETTINGS with PCB manufacturing rules:

Field Description

Field	Description
`MINROUTEWIDTH`	Minimum (thin) route width
`MINNECKED`	Minimum thinner track length
`MINUNNECKED`	Minimum thicker track length
`MINMITER`	Minimum mitre (not enforced by CADSTAR)
`MAXMITER`	Maximum mitre (not enforced by CADSTAR)
`MAXPHYSLAYER`	Maximum physical layer number (must be >= number of copper layers)
`TRACKGRID`	Track routing grid (equal X and Y)
`VIAGRID`	Via placement grid (equal X and Y)
`BACKOFFJUNCTIONS`	Back off at junctions flag
`BACKOFFWIDTHCHANGE`	Back off at width changes flag

MINROUTEWIDTH

Minimum (thin) route width

MINNECKED

Minimum thinner track length

MINUNNECKED

Minimum thicker track length

MINMITER

Minimum mitre (not enforced by CADSTAR)

MAXMITER

Maximum mitre (not enforced by CADSTAR)

MAXPHYSLAYER

Maximum physical layer number (must be >= number of copper layers)

TRACKGRID

Track routing grid (equal X and Y)

VIAGRID

Via placement grid (equal X and Y)

BACKOFFJUNCTIONS

Back off at junctions flag

BACKOFFWIDTHCHANGE

Back off at width changes flag

Component Definitions (SYMDEF for PCB)

PCB symbol definitions extend the common SYMDEF with component-specific structures:

(SYMDEF "SD1" "RESISTOR_0805" ""
  (PT 0 0)              ;; Origin
  (SYMHEIGHT 100000)     ;; 3D component height
  (PAD 1 (PT -45000 0) "PC1" "MINIMUM"
    (EXITS ...)
    (PINIDENTIFIER "1")
    (FIRSTPAD)
  )
  (PAD 2 (PT 45000 0) "PC1" "MINIMUM"
    (EXITS ...)
    (PINIDENTIFIER "2")
  )
  (COMPCOPPER ...)
  (COMPAREA ...)
  (FIGURE ...)
)

Field Description

Field	Description
`SYMHEIGHT`	3D component height in z direction
`PAD`	Component pad: `attr0`=PAD_ID, position, PADCODE_ID, side
`COMPCOPPER`	Copper shape in the component footprint, may be associated with pad IDs
`COMPAREA`	Component area (placement, keepout, no-tracks, no-vias constraints)
`DIMENSION`	Dimension annotations within the component

SYMHEIGHT

3D component height in z direction

PAD

Component pad: attr0=PAD_ID, position, PADCODE_ID, side

COMPCOPPER

Copper shape in the component footprint, may be associated with pad IDs

COMPAREA

Component area (placement, keepout, no-tracks, no-vias constraints)

DIMENSION

Dimension annotations within the component

Pad Side

Keyword Description

Keyword	Description
`MINIMUM`	Physical layer 1 (front/top), used for SMD
`MAXIMUM`	Highest physical layer (back/bottom), used for SMD
`THROUGH`	All physical layers, through-hole

MINIMUM

Physical layer 1 (front/top), used for SMD

MAXIMUM

Highest physical layer (back/bottom), used for SMD

THROUGH

All physical layers, through-hole

Component Types

The SYMDEF type is inferred from the reference name:

Type Recognition Rule

Type	Recognition Rule
`COMPONENT`	Standard component (default)
`JUMPER`	Reference name starts with `JUMPERNF` and has exactly two pads
`STARPOINT`	Reference name starts with `STARPOINTNF`; all pads must share the same position, orientation, side, pad code, and exit direction
`TESTPOINT`	Reference name equals `TESTPOINT`; limited to one pad

COMPONENT

Standard component (default)

JUMPER

Reference name starts with JUMPERNF and has exactly two pads

STARPOINT

Reference name starts with STARPOINTNF; all pads must share the same position, orientation, side, pad code, and exit direction

TESTPOINT

Reference name equals TESTPOINT; limited to one pad

Components (Instances)

(COMPONENT "C1" "R1" "P1" "SD1"
  (PT 500000 300000)
  (ORIENT 900000)
  (MIRROR)
  (TEXTLOC ...)
  (ATTR ...)
  (PINLABEL ...)
  (PINATTR ...)
  (PADEXCEPTION ...)
)

Field Description

Field	Description
`attr0`	COMPONENT_ID
`attr1`	Designator (e.g. "R1")
`attr2`	PART_ID
`attr3`	SYMDEF_ID
`PT`	Placement origin
`ORIENT`	Orientation angle (1/1000 degree)
`MIRROR`	Present if component is mirrored
`TESTPOINT`	Present if component is a testpoint
`TEXTLOC`	Attribute display locations
`PINLABEL`	Per-pin label overrides (may differ from parts library)
`PINATTR`	Per-pin attributes and testland side
`PADEXCEPTION`	Per-instance pad code, exit, side, or orientation overrides

attr0

COMPONENT_ID

attr1

Designator (e.g. "R1")

attr2

PART_ID

attr3

SYMDEF_ID

PT

Placement origin

ORIENT

Orientation angle (1/1000 degree)

MIRROR

Present if component is mirrored

TESTPOINT

Present if component is a testpoint

TEXTLOC

Attribute display locations

PINLABEL

Per-pin label overrides (may differ from parts library)

PINATTR

Per-pin attributes and testland side

PADEXCEPTION

Per-instance pad code, exit, side, or orientation overrides

Nets (PCB)

PCB nets contain richer routing data than schematic nets:

Node ID Prefix Description

Node	ID Prefix	Description
`PIN`	`P`	Pad in a PCB component: COMPONENT_ID + PAD_ID
`JPT`	`J`	Junction point with optional TRUNKREF
`VIA`	`V`	Via instance: VIACODE_ID + LAYERPAIR_ID + location
`COPTERM`	`CT`	Copper terminal: COPPER_ID + terminal number
`CONN`	—	Connection between two net elements, containing a ROUTE or UNROUTE

PIN

P

Pad in a PCB component: COMPONENT_ID + PAD_ID

JPT

J

Junction point with optional TRUNKREF

VIA

V

Via instance: VIACODE_ID + LAYERPAIR_ID + location

COPTERM

CT

Copper terminal: COPPER_ID + terminal number

CONN

—

Connection between two net elements, containing a ROUTE or UNROUTE

Routes

(CONN "P1" "P2" "RC1"
  (ROUTE "LAY1"
    (PT 100000 200000)
    (ROUTEWIDTH 25000)
    (PT 100000 300000)
    (ROUTEWIDTH 15000)
    (CWARC
      (PT 110000 310000)
      (PT 120000 300000)
    )
  )
)

A ROUTE contains an initial layer, a start point, and a sequence of route vertices. Each vertex is preceded by a ROUTEWIDTH node that sets the track width for that segment. Width can change along a single route.

Route vertices may include TDSTART / TDEND (teardrop at start/end) and FIXED flags.

An UNROUTE token (instead of ROUTE) with a layer ID indicates a connection via a power plane layer rather than an explicit track.

Templates (Copper Pour Zones)

Templates define the rules for copper pour and are linked to poured copper shapes:

(TEMPLATE "T1" "LC1" "GND_POUR" "N1" "LAY1"
  (POURING "CC1" "CC2"
    (CLEARANCE 20000)
    (SLIVERWIDTH 10000)
    (ADDITIONALISO 5000)
    (RELIEFPADSANG 450000)
    (RELIEFVIASANG 450000)
    (FILLED)
    (REGENERATE)
  )
  (OUTLINE ...)
)

Pouring Parameter Description

Pouring Parameter	Description
`attr0`	Copper code for outline/fill
`attr1`	Relief copper code for thermal reliefs
`CLEARANCE`	Thermal relief clearance around pads
`SLIVERWIDTH`	Minimum copper sliver width
`ADDITIONALISO`	Additional isolation beyond spacing rules
`RELIEFPADSANG`	Thermal relief orientation for pads
`RELIEFVIASANG`	Thermal relief orientation for vias
`MINISOCOP`	Minimum isolated copper island size
`MINDISJCOP`	Minimum disjoint copper island size
`NOPINRELIEF`	Disable thermal relief on pads
`NOVIARELIEF`	Disable thermal relief on vias
`IGNORETRN`	Allow copper in no-routing areas
`BOXPINS`	Box isolated pins
`REGENERATE`	Automatic repour on changes
`AUTOROUTETARGET`	Target for auto-router
`FILLED` or `HATCHED`	Fill type (hatched requires HATCHCODE_ID)
`RELIEFCROSS` or `RELIEFCUTS`	Relief generation method

attr0

Copper code for outline/fill

attr1

Relief copper code for thermal reliefs

CLEARANCE

Thermal relief clearance around pads

SLIVERWIDTH

Minimum copper sliver width

ADDITIONALISO

Additional isolation beyond spacing rules

RELIEFPADSANG

Thermal relief orientation for pads

RELIEFVIASANG

Thermal relief orientation for vias

MINISOCOP

Minimum isolated copper island size

MINDISJCOP

Minimum disjoint copper island size

NOPINRELIEF

Disable thermal relief on pads

NOVIARELIEF

Disable thermal relief on vias

IGNORETRN

Allow copper in no-routing areas

BOXPINS

Box isolated pins

REGENERATE

Automatic repour on changes

AUTOROUTETARGET

Target for auto-router

FILLED or HATCHED

Fill type (hatched requires HATCHCODE_ID)

RELIEFCROSS or RELIEFCUTS

Relief generation method

Copper Objects

COPPER nodes represent the actual poured copper shapes, linked back to templates:

(COPPER "COP1" "CC1" "LAY1"
  (NETREF "N1"
    (COPPERTERM 1 (PT 100000 200000))
    (COPPERTERM 2 (PT 300000 200000))
  )
  (SOLID ...)
  (POUREDTEMPLATEREF "T1")
)

Board Outlines

(BOARD "B1" "LC1"
  (OUTLINE
    (PT 0 0)
    (PT 1000000 0)
    (PT 1000000 500000)
    (PT 0 500000)
    (PT 0 0)
  )
)

Areas

Areas define placement, routing, and keepout regions:

(AREA "A1" "LC1" "Placement Area" "LAY1"
  (OUTLINE ...)
  (PLACEMENT)
  (ROUTING)
  (KEEPOUT)
  (NOTRACKS)
  (NOVIAS)
  (AREAHEIGHT 500000)
  (RULESETREF "RS1")
)

Dimensions

Three dimension types are supported: LINEARDIM, LEADERDIM, and ANGLEDIM. Each contains an arrow definition, text format, extension lines, and a measurement line.

Subtypes include: DIMENSION_ORTHOGONAL, DIMENSION_DIRECT, DIMENSION_ANGLED, DIMENSION_DIAMETER, DIMENSION_RADIUS, DIMENSION_ANGULAR.

Parts

The PARTS node is common to both schematic and PCB archives and maps part definitions to symbol/footprint references with pin-level detail.

(PART "P1" "RES_100K" 1
  (PARTDEFINITION "RES_100K"
    (GATEDEFINITION "A" "RESISTOR" "" 2)
    (PARTDEFINITIONPIN 1
      (PINIDENTIFIER "1")
      (PINNAME "1")
      (PINLABEL "~")
      (PINTERM "A" 1)
      (PINTYPE "UNCOMMITTED")
      (PINPOSITION 0)
    )
    (PARTDEFINITIONPIN 2
      (PINIDENTIFIER "2")
      (PINNAME "2")
      (PINLABEL "~")
      (PINTERM "A" 2)
    )
    (PINEQUIVALENCE 1 2)
    (SWAPGROUP ...)
    (HIDEPINNAMES)
  )
  (PARTPIN 1 ...)
  (PARTPIN 2 ...)
)

Part Definition

Field Description

Field	Description
`GATEDEFINITION`	Gate: `attr0`=GATE_ID (e.g. "A"), `attr1`=symbol name, `attr2`=alternate, `attr3`=pin count
`PARTDEFINITIONPIN`	Pin: `attr0`=pin ID. Children: `PINIDENTIFIER`, `PINNAME`, `PINLABEL`, `PINSIGNAL`, `PINTERM`, `PINTYPE`, `PINLOAD`, `PINPOSITION`
`PINEQUIVALENCE`	List of swappable pin IDs
`SWAPGROUP`	Gate swap group with swap gates
`HIDEPINNAMES`	Do not display pin names on the schematic symbol
`MAXPINCOUNT`	Maximum electrical pin count

GATEDEFINITION

Gate: attr0=GATE_ID (e.g. "A"), attr1=symbol name, attr2=alternate, attr3=pin count

PARTDEFINITIONPIN

Pin: attr0=pin ID. Children: PINIDENTIFIER, PINNAME, PINLABEL, PINSIGNAL, PINTERM, PINTYPE, PINLOAD, PINPOSITION

PINEQUIVALENCE

List of swappable pin IDs

SWAPGROUP

Gate swap group with swap gates

HIDEPINNAMES

Do not display pin names on the schematic symbol

MAXPINCOUNT

Maximum electrical pin count

Pin Types

Keyword Description

Keyword	Description
`UNCOMMITTED`	Default, uncommitted
`INPUT`	Input pin
`OUTPUT_OR`	Output, OR-tieable
`OUTPUT_NOT_OR`	Output, not OR-tieable
`OUTPUT_NOT_NORM_OR`	Output, not normally OR-tieable
`POWER`	Power pin
`GROUND`	Ground pin
`TRISTATE_BIDIR`	Tristate bidirectional
`TRISTATE_INPUT`	Tristate input
`TRISTATE_DRIVER`	Tristate output

UNCOMMITTED

Default, uncommitted

INPUT

Input pin

OUTPUT_OR

Output, OR-tieable

OUTPUT_NOT_OR

Output, not OR-tieable

OUTPUT_NOT_NORM_OR

Output, not normally OR-tieable

POWER

Power pin

GROUND

Ground pin

TRISTATE_BIDIR

Tristate bidirectional

TRISTATE_INPUT

Tristate input

TRISTATE_DRIVER

Tristate output

Pin Name Position

Value Quadrant

Value	Quadrant
`0`	Top right (default)
`1`	Top left
`2`	Bottom left
`3`	Bottom right

0

Top right (default)

1

Top left

2

Bottom left

3

Bottom right

Parts Library Format (.lib)

The .lib file uses a line-oriented text format distinct from the archive S-expression format. It is parsed using a PEGTL (Parsing Expression Grammar Template Library) grammar defined in cadstar_parts_lib_grammar.h.

File Structure

# FORMAT 32
+N0 'root' 'part1' 'part2'
+N1 N0 'subnode1' 'part3'
.RESISTOR_100K (1234):1 ;100K 1% Resistor
RES_0805 (RES_ALT)
*VALUE 100K
*DFN RES_100K
*STM R
*PNM 1=A1 2=A2
*PLB 1=~ 2=~
*EQU 1=2
$Param1(Value1)
%PCBattr(AttrVal)
@SharedAttr(BothVal)
~LibAttr(SearchVal)
RESISTOR
1.0 2.0
/VCC 3.0
.END

FORMAT Header

The first line may contain # FORMAT 32 specifying the file format version. Some older files omit this and begin directly with part definitions.

Hierarchy Nodes

Lines beginning with + define a tree-structured hierarchy for organizing parts:

+N<index> [N<parent_index>] '<node_name>' ['<part_name>' ...]

The & character at end of line indicates line continuation.

Part Entry Structure

Each part begins with a header line starting with .:

.<Part Name>[ (<Part Number>)][:<Part Version>][;<Description>]

The grammar for a complete part entry:

Line Prefix Description

Line Prefix	Description
`.`	Part header with name, optional number/version/description
(no prefix)	PCB component reference name, optional alternate in parentheses
`*VALUE`	Part value string
`*DFN`	Part definition name
`*NGS`	No gate swapping allowed
`*NPV`	Pins not visible
`*STM`	Component name stem (reference designator prefix)
`*MXP`	Maximum pin count
`*SPI`	SPICE model reference
`*PAC`	Part acceptance text
`*PNM`	Pin names: `<ID>=<Name>` pairs (max 10 chars per name)
`*PLB`	Pin labels: `<ID>=<Label>` pairs
`*EQU`	Pin equivalences: `<ID>=<ID>[=<ID>…]` groups separated by commas
`*SYM`	Swap group element name
`*INT`	Internal swap gate: list of pin IDs
`*EXT`	External swap gate: list of pin IDs
`*<name>`	User-defined attribute (ignored by CADSTAR, used by third-party tools)
`$`	Schematic attribute: `$[!]<name>(<value>)`, `!` = read-only
`%`	PCB attribute: `%[!]<name>(<value>)`, `!` = read-only
`@`	Schematic+PCB attribute: `@[!]<name>(<value>)`, `!` = read-only
`~`	Parts library attribute: `~[!]<name>(<value>)`, `!` = read-only

.

Part header with name, optional number/version/description

(no prefix)

PCB component reference name, optional alternate in parentheses

*VALUE

Part value string

*DFN

Part definition name

*NGS

No gate swapping allowed

*NPV

Pins not visible

*STM

Component name stem (reference designator prefix)

*MXP

Maximum pin count

*SPI

SPICE model reference

*PAC

Part acceptance text

*PNM

Pin names: <ID>=<Name> pairs (max 10 chars per name)

*PLB

Pin labels: <ID>=<Label> pairs

*EQU

Pin equivalences: <ID>=<ID>[=<ID>…] groups separated by commas

*SYM

Swap group element name

*INT

Internal swap gate: list of pin IDs

*EXT

External swap gate: list of pin IDs

*<name>

User-defined attribute (ignored by CADSTAR, used by third-party tools)

$

Schematic attribute: $[!]<name>(<value>), ! = read-only

%

PCB attribute: %[!]<name>(<value>), ! = read-only

@

Schematic+PCB attribute: @[!]<name>(<value>), ! = read-only

~

Parts library attribute: ~[!]<name>(<value>), ! = read-only

After the attribute lines, symbol entries list the schematic symbol references and their pin assignments:

<Symbol Refname>[ (<Alternate>)]
<PinID>.<Position>[!<PinType>][:<Loading>] [...]

Hidden pins (power/ground connections) follow the symbol entries:

/<SignalName> <PinID>.<Position>[!<PinType>][:<Loading>] [...]

Pin Entry Fields

Each pin entry in the symbol section has the format <ID>.<Position>[!<Type>][:<Load>]:

Field	Description
ID	Pin identifier (integer)
Position	Quadrant 0-3 for pin name placement
Type	Optional pin electrical type (alpha characters)
Load	Optional electrical loading value (integer)

Field

Description

Pin identifier (integer)

Position

Quadrant 0-3 for pin name placement

Type

Optional pin electrical type (alpha characters)

Load

Optional electrical loading value (integer)

PEGTL Grammar Overview

The parser uses PEGTL grammar rules. Key non-terminals:

Rule Purpose

Rule	Purpose
`GRAMMAR`	Top-level: optional FORMAT, hierarchy nodes, part entries, optional `.END`
`PART_ENTRY`	Complete part: header, PCB component, attributes, symbols, hidden pins
`PART_HEADER`	`.` prefix, name, optional number/version/description
`SYMBOL_ENTRY`	Symbol reference name + pin list
`HIDDEN_PIN_ENTRY`	`/` prefix signal name + pin list
`PIN_ENTRY`	`<ID>.<Position>[!<Type>][:<Load>]`
`VALID_HEADER`	File validation: FORMAT line or part header within first 5 lines

GRAMMAR

Top-level: optional FORMAT, hierarchy nodes, part entries, optional .END

PART_ENTRY

Complete part: header, PCB component, attributes, symbols, hidden pins

PART_HEADER

. prefix, name, optional number/version/description

SYMBOL_ENTRY

Symbol reference name + pin list

HIDDEN_PIN_ENTRY

/ prefix signal name + pin list

PIN_ENTRY

<ID>.<Position>[!<Type>][:<Load>]

VALID_HEADER

File validation: FORMAT line or part header within first 5 lines

Line continuation with & at end of line is supported throughout. The ? character in *VALUE fields represents a newline within the value string.

Common Data Types

Text Fields

CADSTAR text objects support embedded field tokens in the format <@[FIELD_NAME][FIELD_VALUE]@>. Known field names:

CADSTAR Field KiCad Variable

CADSTAR Field	KiCad Variable
`DESIGN TITLE`	`DESIGN_TITLE`
`SHORT JOBNAME`	`SHORT_JOBNAME`
`LONG JOBNAME`	`LONG_JOBNAME`
`NUM_OF_SHEETS`	`##`
`SHEET_NUMBER`	`#`
`SHEET_NAME`	`SHEETNAME`
`VARIANT_NAME`	`VARIANT_NAME`
`VARIANT_DESCRIPTION`	`VARIANT_DESCRIPTION`
`REG_USER`	`REG_USER`
`COMPANY_NAME`	`COMPANY_NAME`
`CURRENT_USER`	`CURRENT_USER`
`DATE`	`DATE`
`TIME`	`TIME`
`MACHINE_NAME`	`MACHINE_NAME`
`FROM_FILE`	Mapped to `FROM_FILE_[filename]_[ext]` variable
`HYPERLINK`	Stored but not rendered (KiCad lacks hyperlink support)

DESIGN TITLE

DESIGN_TITLE

SHORT JOBNAME

SHORT_JOBNAME

LONG JOBNAME

LONG_JOBNAME

NUM_OF_SHEETS

##

SHEET_NUMBER

#

SHEET_NAME

SHEETNAME

VARIANT_NAME

VARIANT_DESCRIPTION

REG_USER

COMPANY_NAME

CURRENT_USER

DATE

TIME

MACHINE_NAME

FROM_FILE

Mapped to FROM_FILE_[filename]_[ext] variable

HYPERLINK

Stored but not rendered (KiCad lacks hyperlink support)

Text Alignment

Value Description

Value	Description
`NO_ALIGNMENT`	Legacy default; behaves as bottom-left of first line in most cases
`TOPLEFT`	Top left of text block
`TOPCENTER`	Top center
`TOPRIGHT`	Top right
`CENTERLEFT`	Center left
`CENTERCENTER`	Center center
`CENTERRIGHT`	Center right
`BOTTOMLEFT`	Bottom left of entire text block
`BOTTOMCENTER`	Bottom center
`BOTTOMRIGHT`	Bottom right

NO_ALIGNMENT

Legacy default; behaves as bottom-left of first line in most cases

TOPLEFT

Top left of text block

TOPCENTER

Top center

TOPRIGHT

Top right

CENTERLEFT

Center left

CENTERCENTER

Center center

CENTERRIGHT

Center right

BOTTOMLEFT

Bottom left of entire text block

BOTTOMCENTER

Bottom center

BOTTOMRIGHT

Bottom right

Justification

Multiline text justification (no effect on single-line text):

LEFT
CENTER
RIGHT

Readability

Text readability direction for vertical text:

BOTTOM_TO_TOP — rotated 90 degrees anticlockwise (default)
TOP_TO_BOTTOM — rotated 90 degrees clockwise

Line Styles

Keyword Style

Keyword	Style
`SOLID`	Solid line
`DASH`	Dashed
`DASHDOT`	Dash-dot
`DASHDOTDOT`	Dash-dot-dot (maps to DASHDOT on import)
`DOT`	Dotted

SOLID

Solid line

DASH

Dashed

DASHDOT

Dash-dot

DASHDOTDOT

Dash-dot-dot (maps to DASHDOT on import)

DOT

Dotted

Swap Rules

The swap rule controls visibility based on component mirror state:

Value Description

Value	Description
`NO_SWAP`	Display when unmirrored
`USE_SWAP_LAYER`	Display when mirrored
`BOTH`	Always display (default)

NO_SWAP

Display when unmirrored

USE_SWAP_LAYER

Display when mirrored

BOTH

Always display (default)

Internal Attribute Names

Attribute names enclosed in parentheses are internal CADSTAR attributes. Known internal names include (PartDescription) and (PartDefinitionNameStem). A complete list has not been documented.

Attributes can be prefixed with `Link ` (including the trailing space) to convert a Part Definition Attribute into a hyperlink.

Font System

CADSTAR fonts are rendered on a 24x24 integer matrix. Character widths range from 12 to 24 units; height is fixed at 24. The default font uses y=5 as the baseline offset for capital letters, leaving space for descenders. The text height ratio used for conversion is (24 - 5) / 24 = 0.7917.

Font weight constants: 400 = normal, 700 = bold.

Variant Hierarchy

Both archive types contain a VHIERARCHY node within the design section that defines variant relationships. The master variant uses the VMASTER node; derived variants use VARIANT with a parent reference:

(VHIERARCHY
  (VMASTER "V0" "Master" "Base design")
  (VARIANT "V1" "V0" "Test Variant" "For testing")
)

Schematic Import

Imported Elements

Multi-sheet schematics with hierarchical structure (parent/child sheets and blocks)
Symbol definitions with terminals, pin labels, and pin numbers
Component instances with reference designators, part references, and attributes
Nets with wires, junctions, buses, bus terminals, and block terminals
Figures (graphical shapes with solid, dashed, and dotted line styles)
Text elements with text code formatting
Documentation symbols, signal references, and symbol variants
Symbol scaling with arbitrary numerator/denominator
Text variables and design fields
Imported symbols saved to a KiCad project library

Limitations

Pin and gate swap data is not loaded.
Multi-line fields are not supported; a workaround annotation is added.
DASHDOTDOT line style maps to DASHDOT.
Independent text justification is not supported.
The importer is read-only.

PCB Import

Imported Elements

Board stackup with layer mapping through an interactive dialog
Material properties (permittivity, loss tangent)
Component library footprints with pads, copper, areas, and figures
Component placement with orientation and mirroring
Pad shapes (annulus, bullet, circle, diamond, finger, octagon, rectangle, rounded rectangle, square) with drill, slot, and layer side properties
Via definitions with drill and shape, layer pairs
Net routing with tracks and route vertices, including width changes along routes
Copper pour zones from templates with thermal relief, hatching, and fill settings
Board outlines
Rule areas (placement, routing, keepout, no-tracks, no-vias)
Design rules (spacing codes with per-layer reassignments)
Dimensions (linear, leader)
Text elements with font settings
Net classes and spacing classes
Drill tables and text variables

Limitations

CADSTAR COPPER objects load as graphical polygons without net association.
Teardrops are parsed but not imported.
Per-layer pad shape overrides and custom padstacks are not fully handled.
Radius and diameter dimensions load as leader dimensions; angular dimensions are not imported.
Placement areas, board attributes, reuse blocks, and swap rules are not processed.
Only a subset of CADSTAR design rules is imported.
Material resistivity is not loaded.

Undocumented Areas

Several parts of the CADSTAR format remain incompletely understood:

TRUNK structure — The TRUNK node in the PCB layout is parsed but its internal structure beyond the ID and a definition string is not fully decoded. Trunks appear to define bus-like routing constructs. Junctions and vias reference them through TRUNKREF.
SYMBOLVARIANT types — The schematic SYMBOLVARIANT node supports GLOBALSIGNAL, SIGNALREF, and TESTPOINT types. Additional variant types may exist.
Internal attribute names — Attributes with names in parentheses (e.g. (PartDescription)) are internal CADSTAR attributes. The full set of internal attribute names is unknown.
Resolution variants — Only METRIC HUNDREDTH MICRON resolution has been observed. Other base units (e.g., imperial) may exist but have not been encountered.
DEFAULTS and DISPLAY sections — These contain CADSTAR configuration data (default shapes, text settings, layer colors, element visibility) that is not currently parsed for import. Future work could extract useful defaults from these sections.
Reuse blocks — The REUSEBLOCK structure stores references to external .pcb files for design reuse. The importer records these but does not resolve or load the referenced files.