Eagle

Introduction

Autodesk Eagle (formerly CadSoft Eagle) is an EDA tool that stores schematics, board layouts, and component libraries in XML files. Prior to version 6.0, Eagle used a proprietary binary format; version 6.0 and later switched to the XML format documented here. KiCad’s importer only accepts XML-format files and rejects binary-format files from earlier versions.

Supported file extensions:

Extension Content

Extension	Content
`.sch`	Schematic
`.brd`	Board / PCB layout
`.lbr`	Library (symbols, packages, and device sets)

.sch

Schematic

.brd

Board / PCB layout

.lbr

Library (symbols, packages, and device sets)

All three file types share the same top-level XML schema. The root element is always <eagle> with a version attribute, containing a single <drawing> element whose content varies by file type. The format is defined by an internal DTD (eagle.dtd) that ships with Eagle (typically found in the Eagle installation directory) but is not embedded in the XML files themselves.

XML Document Structure

Every Eagle XML file follows the same top-level structure:

<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="9.6.2">                               (1)
  <compatibility>                                      (2)
    <note version="6.0" severity="warning">...</note>
  </compatibility>
  <drawing>                                            (3)
    <settings>...</settings>                           (4)
    <grid .../>                                        (5)
    <filters>...</filters>                             (6)
    <layers>                                           (7)
      <layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
      ...
    </layers>
    <!-- exactly one of: <schematic>, <board>, or <library> -->
    <schematic>...</schematic>                          (8)
  </drawing>
</eagle>

1	Root element. The `version` attribute is formatted as `major.minor.patch` despite the DTD declaring it as `%Real`.
2	Optional compatibility notes. Each `<note>` carries the Eagle version that introduced the incompatibility and a severity (`warning` or `error`).
3	The `<drawing>` container holds all visual and electrical content.
4	Optional `<settings>` with font and text direction preferences.
5	Optional `<grid>` defining the editor grid configuration.
6	Optional `<filters>` with named filter expressions.
7	Required `<layers>` section defining all available layers.
8	Exactly one of `<schematic>`, `<board>`, or `<library>` appears here, depending on the file type.

Element Tree Overview

eagle
 +-- compatibility?
 |    +-- note*
 +-- drawing
      +-- settings?
      |    +-- setting*
      +-- grid?
      +-- filters?
      |    +-- filter*
      +-- layers
      |    +-- layer*
      +-- schematic | board | library    (exactly one)

Layer Definitions

The <layers> section appears in every Eagle file. Each <layer> element maps a numeric layer ID to a name, display color, and fill pattern.

<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>

Table 1. `<layer>` attributes
Attribute	Type	Required	Description
`number`	`%Layer`	yes	Integer layer ID
`name`	`%String`	yes	Human-readable layer name
`color`	`%Int`	yes	Display color index
`fill`	`%Int`	yes	Fill pattern index
`visible`	`%Bool`	no	Layer visibility (default `"yes"`)
`active`	`%Bool`	no	Layer active state (default `"yes"`)

Board Layer Number Table

The following table shows Eagle’s fixed layer numbers, their canonical names, and the default KiCad layer each maps to during import.

Eagle #	Eagle Name	KiCad Layer
1	Top	F.Cu
2	Route2	In1.Cu
3	Route3	In2.Cu
4-14	Route4-Route14	In3.Cu through In13.Cu
15	Route15	In14.Cu
16	Bottom	B.Cu
17	Pads	(multi-layer pad handling)
18	Vias	(multi-layer via handling)
19	Unrouted	Dwgs.User
20	Dimension	Edge.Cuts (required mapping)
21	tPlace	F.SilkS
22	bPlace	B.SilkS
23	tOrigins	(not mapped)
24	bOrigins	(not mapped)
25	tNames	F.SilkS
26	bNames	B.SilkS
27	tValues	F.Fab
28	bValues	B.Fab
29	tStop	F.Mask
30	bStop	B.Mask
31	tCream	F.Paste
32	bCream	B.Paste
33	tFinish	F.Mask
34	bFinish	B.Mask
35	tGlue	F.Adhes
36	bGlue	B.Adhes
37	tTest	UNDEFINED_LAYER
38	bTest	UNDEFINED_LAYER
39	tKeepout	F.CrtYd
40	bKeepout	B.CrtYd
41	tRestrict	(keepout zone on F.Cu)
42	bRestrict	(keepout zone on B.Cu)
43	vRestrict	(keepout zone on all Cu)
44	Drills	(not mapped)
45	Holes	UNDEFINED_LAYER
46	Milling	UNDEFINED_LAYER
47	Measures	(not mapped)
48	Document	Cmts.User
49	ReferenceLC	Cmts.User
50	ReferenceLS	Cmts.User
51	tDocu	F.Fab
52	bDocu	B.Fab
91	Nets	(schematic only)
92	Busses	(schematic only)
93	Pins	(schematic only)
94	Symbols	(schematic only)
95	Names	(schematic only)
96	Values	(schematic only)
97	Info	(schematic only)
98	Guide	(schematic only)
160	UserLayer1	Eco1.User
161	UserLayer2	Eco2.User

Eagle #

Eagle Name

KiCad Layer

Top

F.Cu

Route2

In1.Cu

Route3

In2.Cu

4-14

Route4-Route14

In3.Cu through In13.Cu

Route15

In14.Cu

Bottom

B.Cu

Pads

(multi-layer pad handling)

Vias

(multi-layer via handling)

Unrouted

Dwgs.User

Dimension

Edge.Cuts (required mapping)

tPlace

F.SilkS

bPlace

B.SilkS

tOrigins

(not mapped)

bOrigins

(not mapped)

tNames

F.SilkS

bNames

B.SilkS

tValues

F.Fab

bValues

B.Fab

tStop

F.Mask

bStop

B.Mask

tCream

F.Paste

bCream

B.Paste

tFinish

F.Mask

bFinish

B.Mask

tGlue

F.Adhes

bGlue

B.Adhes

tTest

UNDEFINED_LAYER

bTest

UNDEFINED_LAYER

tKeepout

F.CrtYd

bKeepout

B.CrtYd

tRestrict

(keepout zone on F.Cu)

bRestrict

(keepout zone on B.Cu)

vRestrict

(keepout zone on all Cu)

Drills

(not mapped)

Holes

UNDEFINED_LAYER

Milling

UNDEFINED_LAYER

Measures

(not mapped)

Document

Cmts.User

ReferenceLC

Cmts.User

ReferenceLS

Cmts.User

tDocu

F.Fab

bDocu

B.Fab

Nets

(schematic only)

Busses

(schematic only)

Pins

(schematic only)

Symbols

(schematic only)

Names

(schematic only)

Values

(schematic only)

Info

(schematic only)

Guide

(schematic only)

160

UserLayer1

Eco1.User

161

UserLayer2

Eco2.User

Layers 37 (tTest), 38 (bTest), 45 (Holes), and 46 (Milling) are mapped to UNDEFINED_LAYER, meaning content on these layers may be lost during import. The interactive layer re-mapping dialog allows the user to override all non-required default mappings.

Schematic Format (`.sch`)

A schematic file contains a <schematic> element inside <drawing>.

Schematic Element Hierarchy

schematic
 +-- description?
 +-- libraries?
 |    +-- library*           (embedded library definitions)
 +-- attributes?
 |    +-- attribute*         (global schematic attributes)
 +-- variantdefs?
 |    +-- variantdef*
 +-- classes?
 |    +-- class*
 +-- modules?
 |    +-- module*            (hierarchical module definitions)
 +-- groups?
 |    +-- schematic_group*
 +-- parts?
 |    +-- part*              (component instances)
 +-- sheets?
 |    +-- sheet*
 +-- errors?
      +-- approved*

<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">  (1)
  <libraries>...</libraries>
  <parts>
    <part name="R1" library="rcl" deviceset="R-US_" device="0805"
          technology="" value="10k"/>                       (2)
  </parts>
  <sheets>
    <sheet>...</sheet>                                       (3)
  </sheets>
</schematic>

1	Optional cross-reference label format strings.
2	Each `<part>` references a library, device set, and device to fully identify a component.
3	Sheets contain the graphical and electrical content.

Part Element (`<part>`)

A part is the fundamental component reference in the schematic. It links to a library’s device set and selects a specific device variant and technology.

Table 2. `<part>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Reference designator (e.g. `R1`, `U3`)
`library`	`%String`	yes	Name of the containing library
`library_urn`	`%Urn`	no	URN for online/managed libraries
`deviceset`	`%String`	yes	Device set name within the library
`device`	`%String`	yes	Specific device (package variant) name
`package3d_urn`	`%Urn`	no	3D package URN
`override_package3d_urn`	`%Urn`	no	Override 3D package URN
`override_package_urn`	`%Urn`	no	Override package URN
`override_locally_modified`	`%Bool`	no	Whether package was locally modified
`technology`	`%String`	no	Technology variant (default `""`)
`value`	`%String`	no	Component value

Child elements: <attribute>*, <variant>*, <spice>?

Instance Element (`<instance>`)

Instances place a specific gate of a part on a sheet.

Table 3. `<instance>` attributes
Attribute	Type	Required	Description
`part`	`%String`	yes	Reference to a `<part>` name
`gate`	`%String`	yes	Gate name within the device set
`x`	`%Coord`	yes	X position in mm
`y`	`%Coord`	yes	Y position in mm
`smashed`	`%Bool`	no	Whether attribute text is detached (default `"no"`)
`rot`	`%Rotation`	no	Rotation (default `"R0"`; only 0/90/180/270)

Child elements: <attribute>*

Gate Element (`<gate>`)

Gates define how a device set’s symbol units are named and placed.

Table 4. `<gate>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Gate name (e.g. `A`, `B`, `P`)
`symbol`	`%String`	yes	Symbol name from the library
`x`	`%Coord`	yes	X offset in the device set editor
`y`	`%Coord`	yes	Y offset in the device set editor
`addlevel`	`%GateAddLevel`	no	When this gate is added (default `"next"`)
`swaplevel`	`%Int`	no	Swap level for gate swapping (default `"0"`)

The addlevel values control when a gate appears:

Value Meaning

Value	Meaning
`must`	Always placed when component is added
`can`	Can be added but is not placed automatically
`next`	Added with the next available unit
`request`	Only added when explicitly requested
`always`	Always present, cannot be removed

must

Always placed when component is added

can

Can be added but is not placed automatically

next

Added with the next available unit

request

Only added when explicitly requested

always

Always present, cannot be removed

Device Set Element (`<deviceset>`)

A device set groups related gates and maps them to package variants.

Table 5. `<deviceset>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Device set name
`urn`	`%Urn`	no	URN identifier
`locally_modified`	`%Bool`	no	Local modification flag
`prefix`	`%String`	no	Reference prefix (e.g. `R`, `C`, `U`)
`uservalue`	`%Bool`	no	Whether user can edit the value
`library_version`	`%Int`	no	Managed library version
`library_locally_modified`	`%Bool`	no	Whether library copy was modified

Child elements: <description>?, <gates>, <devices>, <spice>?

Connect Element (`<connect>`)

Connects map schematic symbol pins to physical package pads.

Table 6. `<connect>` attributes
Attribute	Type	Required	Description
`gate`	`%String`	yes	Gate name
`pin`	`%String`	yes	Pin name in the symbol
`pad`	`%String`	yes	Pad name(s) in the package (space-separated for multi-pad)
`route`	`%ContactRoute`	no	Routing constraint (default `"all"`)

Sheet Element (`<sheet>`)

sheet
 +-- description?
 +-- plain?              (graphical-only elements)
 +-- moduleinsts?        (hierarchical module instances)
 +-- instances?          (component gate placements)
 +-- busses?
 |    +-- bus*
 |         +-- segment*
 +-- nets?
      +-- net*
           +-- segment*

Each sheet’s <nets> section contains net connectivity. A <net> contains <segment> elements, each of which holds the wires, junctions, labels, pin references, and port references that define a contiguous piece of the net.

Segment Element (`<segment>`)

segment
 +-- pinref*     (only valid in <net> context)
 +-- portref*    (module port references)
 +-- wire*
 +-- junction*
 +-- label*
 +-- probe*

Module Element (`<module>`)

Modules implement Eagle’s hierarchical design capability. A module defines its own parts, sheets, and ports, and is instantiated via <moduleinst> elements on a parent sheet.

Table 7. `<module>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Module name
`prefix`	`%String`	no	Reference prefix for parts inside
`dx`	`%Coord`	yes	Module rectangle width
`dy`	`%Coord`	yes	Module rectangle height

Child elements: <description>?, <ports>?, <variantdefs>?, <groups>?, <parts>?, <sheets>?

Port Element (`<port>`)

Ports define the interface pins of a module.

Table 8. `<port>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Port name
`side`	`%String`	yes	Side of module rectangle (`"top"`, `"bottom"`, `"left"`, `"right"`)
`coord`	`%Coord`	yes	Position along the specified side
`direction`	`%PortDirection`	no	Electrical direction (default `"io"`)

The DTD incorrectly defines side as an integer. In practice it is a string with values "top", "bottom", "left", and "right".

Pin Direction Values

Eagle pin and port directions are string values mapped to electrical types during import.

Eagle Value Meaning KiCad Pin Type

Eagle Value	Meaning	KiCad Pin Type
`in`	Input	`PT_INPUT`
`out`	Output	`PT_OUTPUT`
`io`	Bidirectional (default)	`PT_BIDI`
`oc`	Open collector	`PT_OPENCOLLECTOR`
`pas`	Passive	`PT_PASSIVE`
`hiz`	High impedance / tri-state	`PT_TRISTATE`
`sup`	Power supply	`PT_POWER_IN`
`pwr`	Power supply (alternate)	`PT_POWER_IN`
`nc`	Not connected	`PT_NC`

in

Input

PT_INPUT

out

Output

PT_OUTPUT

io

Bidirectional (default)

PT_BIDI

oc

Open collector

PT_OPENCOLLECTOR

pas

Passive

PT_PASSIVE

hiz

High impedance / tri-state

PT_TRISTATE

sup

Power supply

PT_POWER_IN

pwr

Power supply (alternate)

PT_POWER_IN

nc

Not connected

PT_NC

Board Format (`.brd`)

A board file contains a <board> element inside <drawing>.

Board Element Hierarchy

board
 +-- description?
 +-- plain?                 (graphical elements not in any signal)
 +-- libraries?
 |    +-- library*
 +-- attributes?
 +-- variantdefs?
 +-- classes?               (net classes with clearance rules)
 |    +-- class*
 +-- designrules?           (manufacturing constraints)
 |    +-- param*
 +-- autorouter?
 +-- elements?              (component placements)
 |    +-- element*
 +-- signals?               (copper connectivity)
      +-- signal*
           +-- contactref*
           +-- wire*
           +-- via*
           +-- polygon*

Element (Component Placement)

The <element> is the board-level equivalent of a schematic <part> combined with placement information.

Table 9. `<element>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Reference designator
`library`	`%String`	yes	Source library name
`library_urn`	`%Urn`	no	Online library URN
`package`	`%String`	yes	Package (footprint) name
`package3d_urn`	`%Urn`	no	3D model URN
`override_package3d_urn`	`%Urn`	no	Override 3D model URN
`override_package_urn`	`%Urn`	no	Override package URN
`override_locally_modified`	`%Bool`	no	Local modification flag
`value`	`%String`	yes	Component value
`x`	`%Coord`	yes	X position in mm
`y`	`%Coord`	yes	Y position in mm
`locked`	`%Bool`	no	Placement lock (default `"no"`)
`populate`	`%Bool`	no	Assembly populate flag (default `"yes"`)
`smashed`	`%Bool`	no	Text detached from footprint (default `"no"`)
`rot`	`%Rotation`	no	Rotation (default `"R0"`)

Child elements: <attribute>*, <variant>*

Signal Element

A <signal> represents a net on the board. It contains routed copper, vias, and polygon pours.

Table 10. `<signal>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Net name
`class`	`%Class`	no	Net class number (default `"0"`)

Child elements: <contactref>*, <wire>*, <via>*, <polygon>*

Net Class Element (`<class>`)

Net classes define default trace widths, drill sizes, and inter-class clearance rules.

Table 11. `<class>` attributes
Attribute	Type	Required	Description
`number`	`%Class`	yes	Class number (0 is the default class)
`name`	`%String`	yes	Class name
`width`	`%Dimension`	no	Default trace width (default `"0"`)
`drill`	`%Dimension`	no	Default drill size (default `"0"`)

Each <class> may contain <clearance> child elements specifying minimum clearance to other net classes:

<class number="1" name="Power" width="0.3" drill="0.4">
  <clearance class="0" value="0.2"/>
  <clearance class="1" value="0.25"/>
</class>

KiCad writes inter-class clearance rules to a .kicad_dru custom design rules file because KiCad’s native net class model does not support per-pair clearance overrides.

Design Rules

Design rules appear as <param> elements within <designrules>. Each parameter is a name/value pair. The KiCad importer parses the following subset:

<designrules name="default">
  <param name="psElongationLong" value="100"/>
  <param name="mvStopFrame" value="1"/>
  ...
</designrules>

Table 12. Design rule parameters parsed by KiCad
Parameter Name	Default	Description
`psElongationLong`	`100`	Pad elongation for "long" shape, percent over 100%
`psElongationOffset`	`0`	Hole offset within elongated pad
`mvStopFrame`	`1.0`	Solder mask expansion, percent of smaller pad dimension
`mvCreamFrame`	`0.0`	Solder paste shrink, percent of smaller pad dimension
`mlMinStopFrame`	`4mil`	Minimum solder mask expansion
`mlMaxStopFrame`	`4mil`	Maximum solder mask expansion
`mlMinCreamFrame`	`0mil`	Minimum solder paste shrink
`mlMaxCreamFrame`	`0mil`	Maximum solder paste shrink
`psTop`	(undef)	Top pad shape override (integer shape enum)
`psBottom`	(undef)	Bottom pad shape override
`psFirst`	(undef)	First pad shape override
`srRoundness`	`0.0`	SMD pad corner rounding, percent
`srMinRoundness`	`0mil`	Minimum corner rounding radius
`srMaxRoundness`	`0mil`	Maximum corner rounding radius
`rvPadTop`	`0.25`	Through-hole pad annulus, ratio of drill diameter
`rlMinPadTop`	`10mil`	Minimum pad annulus
`rlMaxPadTop`	`20mil`	Maximum pad annulus
`rvViaOuter`	`0.25`	Via annulus, ratio of drill diameter
`rlMinViaOuter`	`10mil`	Minimum via annulus
`rlMaxViaOuter`	`20mil`	Maximum via annulus
`mdWireWire`	`0`	Minimum wire-to-wire spacing

Many additional design rule parameters exist in Eagle files (e.g. rlMinViaInner, msWidth, mdPadVia, mdCopperDimension) but are not currently parsed by the KiCad importer.

Library Format (`.lbr`)

Library files use the same top-level XML schema as schematics and boards. The <drawing> element contains a <library> element instead of <schematic> or <board>.

Library Element Hierarchy

library
 +-- description?
 +-- packages?
 |    +-- package*           (footprint definitions)
 +-- packages3d?
 |    +-- package3d*         (3D model references)
 +-- symbols?
 |    +-- symbol*            (schematic symbol definitions)
 +-- devicesets?
      +-- deviceset*         (component definitions linking symbols to packages)

Table 13. `<library>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Library name (only meaningful inside boards/schematics)
`urn`	`%Urn`	no	URN for online/managed libraries

Libraries embedded within .sch or .brd files appear inside a <libraries> container and carry a name attribute. Standalone .lbr files omit the name.

Package Element

A <package> defines a physical footprint.

package
 +-- description?
 +-- polygon*
 +-- wire*
 +-- text*
 +-- dimension*
 +-- circle*
 +-- rectangle*
 +-- frame*
 +-- hole*
 +-- pad*               (through-hole pads)
 +-- smd*               (surface mount pads)

Table 14. `<package>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Package name
`urn`	`%Urn`	no	URN identifier
`locally_modified`	`%Bool`	no	Local modification flag
`library_version`	`%Int`	no	Managed library version
`library_locally_modified`	`%Bool`	no	Library local modification flag

Symbol Element

A <symbol> defines a schematic symbol.

symbol
 +-- description?
 +-- polygon*
 +-- wire*
 +-- text*
 +-- dimension*
 +-- pin*
 +-- circle*
 +-- rectangle*
 +-- frame*

Table 15. `<symbol>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Symbol name
`urn`	`%Urn`	no	URN identifier
`locally_modified`	`%Bool`	no	Local modification flag
`library_version`	`%Int`	no	Managed library version
`library_locally_modified`	`%Bool`	no	Library local modification flag

Common Elements

The following element types are shared across schematics, boards, and libraries.

Wire (`<wire>`)

Wires represent line segments, arcs (when curve is nonzero), and net connections.

Table 16. `<wire>` attributes
Attribute	Type	Required	Description
`x1`	`%Coord`	yes	Start X coordinate
`y1`	`%Coord`	yes	Start Y coordinate
`x2`	`%Coord`	yes	End X coordinate
`y2`	`%Coord`	yes	End Y coordinate
`width`	`%Dimension`	yes	Line width
`layer`	`%Layer`	yes	Layer number
`extent`	`%Extent`	no	Only applicable for airwires
`style`	`%WireStyle`	no	Line style (default `"continuous"`)
`curve`	`%WireCurve`	no	Arc curvature in degrees, range -359.9..359.9 (default `"0"`)
`cap`	`%WireCap`	no	Line cap style (default `"round"`)

Wire style values: continuous, longdash, shortdash, dashdot

Wire cap values: flat, round (cap only applies when curve is nonzero)

Circle (`<circle>`)

Table 17. `<circle>` attributes
Attribute	Type	Required	Description
`x`	`%Coord`	yes	Center X
`y`	`%Coord`	yes	Center Y
`radius`	`%Coord`	yes	Radius
`width`	`%Dimension`	yes	Line width (0 = filled)
`layer`	`%Layer`	yes	Layer number

Rectangle (`<rectangle>`)

Table 18. `<rectangle>` attributes
Attribute	Type	Required	Description
`x1`	`%Coord`	yes	First corner X
`y1`	`%Coord`	yes	First corner Y
`x2`	`%Coord`	yes	Opposite corner X
`y2`	`%Coord`	yes	Opposite corner Y
`layer`	`%Layer`	yes	Layer number
`rot`	`%Rotation`	no	Rotation (default `"R0"`)

Text (`<text>`)

Table 19. `<text>` attributes
Attribute	Type	Required	Description
`x`	`%Coord`	yes	Anchor X position
`y`	`%Coord`	yes	Anchor Y position
`size`	`%Dimension`	yes	Font height
`layer`	`%Layer`	yes	Layer number
`font`	`%TextFont`	no	Font type (default `"proportional"`)
`ratio`	`%Int`	no	Stroke width as percent of height (default `"8"`)
`rot`	`%Rotation`	no	Rotation (default `"R0"`)
`align`	`%Align`	no	Text alignment (default `"bottom-left"`)
`distance`	`%Int`	no	Line spacing percent (default `"50"`)

Font values: vector, proportional, fixed

Alignment values: bottom-left, bottom-center, bottom-right, center-left, center, center-right, top-left, top-center, top-right

Polygon (`<polygon>`)

Polygons are used for copper pours (in signals) and graphical shapes (in packages and schematics).

Table 20. `<polygon>` attributes
Attribute	Type	Required	Description
`width`	`%Dimension`	yes	Outline width
`layer`	`%Layer`	yes	Layer number
`spacing`	`%Dimension`	no	Hatch spacing (for hatch pour)
`pour`	`%PolygonPour`	no	Pour type (default `"solid"`)
`isolate`	`%Dimension`	no	Isolation gap (only in signal/package context)
`orphans`	`%Bool`	no	Keep orphan copper islands (default `"no"`, signal only)
`thermals`	`%Bool`	no	Use thermal relief (default `"yes"`, signal only)
`rank`	`%Int`	no	Pour priority: 1-6 in signal, 0 or 7 in package (default `"0"`)

Pour type values: solid, hatch, cutout

Child elements: <vertex>*

Eagle rank and KiCad priority are inversely related. In Eagle, lower-rank polygons have higher pour priority; in KiCad, higher-priority zones take precedence.

Vertex (`<vertex>`)

Vertices define the corners of polygons and splines.

Table 21. `<vertex>` attributes
Attribute	Type	Required	Description
`x`	`%Coord`	yes	X coordinate
`y`	`%Coord`	yes	Y coordinate
`curve`	`%WireCurve`	no	Arc curvature to next vertex, -359.9..359.9 (default `"0"`)

Dimension (`<dimension>`)

Table 22. `<dimension>` attributes
Attribute	Type	Required	Description
`x1`	`%Coord`	yes	First reference point X
`y1`	`%Coord`	yes	First reference point Y
`x2`	`%Coord`	yes	Second reference point X
`y2`	`%Coord`	yes	Second reference point Y
`x3`	`%Coord`	yes	Text/leader position X
`y3`	`%Coord`	yes	Text/leader position Y
`layer`	`%Layer`	yes	Layer number
`dtype`	`%DimensionType`	no	Dimension type (default `"parallel"`)
`width`	`%Dimension`	no	Line width (default `"0.13"`)
`extwidth`	`%Dimension`	no	Extension line width (default `"0"`)
`extlength`	`%Dimension`	no	Extension line length (default `"0"`)
`extoffset`	`%Dimension`	no	Extension line offset (default `"0"`)
`textsize`	`%Dimension`	yes	Dimension text size
`textratio`	`%Int`	no	Text stroke ratio (default `"8"`)
`unit`	`%GridUnit`	no	Display unit (default `"mm"`)
`precision`	`%Int`	no	Decimal places (default `"2"`)
`visible`	`%Bool`	no	Show dimension value (default `"no"`)

Pin (`<pin>`)

Pins appear in symbol definitions.

Table 23. `<pin>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Pin name
`x`	`%Coord`	yes	Pin endpoint X
`y`	`%Coord`	yes	Pin endpoint Y
`visible`	`%PinVisible`	no	What to display (default `"both"`)
`length`	`%PinLength`	no	Pin stub length (default `"long"`)
`direction`	`%PinDirection`	no	Electrical direction (default `"io"`)
`function`	`%PinFunction`	no	Pin function (default `"none"`)
`swaplevel`	`%Int`	no	Swap level (default `"0"`)
`rot`	`%Rotation`	no	Rotation (default `"R0"`)

Pin visible values: off, pad, pin, both

Pin length values: point, short, middle, long

Pin function values: none, dot, clk, dotclk

Through-Hole Pad (`<pad>`)

Table 24. `<pad>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Pad name
`x`	`%Coord`	yes	X position
`y`	`%Coord`	yes	Y position
`drill`	`%Dimension`	yes	Drill diameter
`diameter`	`%Dimension`	no	Pad diameter (default `"0"`, auto-calculated)
`shape`	`%PadShape`	no	Pad shape (default `"round"`)
`rot`	`%Rotation`	no	Rotation (default `"R0"`)
`stop`	`%Bool`	no	Generate solder mask opening (default `"yes"`)
`thermals`	`%Bool`	no	Use thermal relief (default `"yes"`)
`first`	`%Bool`	no	First pad flag for shape override (default `"no"`)

Pad shape values: square, round, octagon, long, offset

SMD Pad (`<smd>`)

Table 25. `<smd>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Pad name
`x`	`%Coord`	yes	X position
`y`	`%Coord`	yes	Y position
`dx`	`%Dimension`	yes	Width
`dy`	`%Dimension`	yes	Height
`layer`	`%Layer`	yes	Layer (1 = Top, 16 = Bottom)
`roundness`	`%Int`	no	Corner rounding percent (default `"0"`)
`rot`	`%Rotation`	no	Rotation (default `"R0"`)
`stop`	`%Bool`	no	Generate solder mask (default `"yes"`)
`thermals`	`%Bool`	no	Use thermal relief (default `"yes"`)
`cream`	`%Bool`	no	Generate solder paste (default `"yes"`)

Via (`<via>`)

Table 26. `<via>` attributes
Attribute	Type	Required	Description
`x`	`%Coord`	yes	X position
`y`	`%Coord`	yes	Y position
`extent`	`%Extent`	yes	Layer span (e.g. `"1-16"` for through-hole)
`drill`	`%Dimension`	yes	Drill diameter
`diameter`	`%Dimension`	no	Outer diameter (default `"0"`, auto-calculated)
`shape`	`%ViaShape`	no	Via shape (default `"round"`)
`alwaysstop`	`%Bool`	no	Force solder mask opening (default `"no"`)

The extent attribute is formatted as "startLayer-endLayer" using layer IDs, e.g. "1-16" for a through-hole via from Top to Bottom, "1-2" for a blind via from Top to Route2.

Hole (`<hole>`)

Non-plated holes.

Table 27. `<hole>` attributes
Attribute	Type	Required	Description
`x`	`%Coord`	yes	X position
`y`	`%Coord`	yes	Y position
`drill`	`%Dimension`	yes	Drill diameter

Attribute (`<attribute>`)

Attributes are key-value pairs attached to parts, instances, elements, or technologies.

An Eagle <attribute> XML element is distinct from an XML attribute on an element. The <attribute> is a full child element with its own position, size, and display properties.

Table 28. `<attribute>` attributes
Attribute	Type	Required	Description
`name`	`%String`	yes	Attribute name
`value`	`%String`	no	Attribute value
`x`	`%Coord`	no	Display X position
`y`	`%Coord`	no	Display Y position
`size`	`%Dimension`	no	Text size
`layer`	`%Layer`	no	Layer number
`font`	`%TextFont`	no	Font type
`ratio`	`%Int`	no	Stroke ratio
`rot`	`%Rotation`	no	Rotation (default `"R0"`)
`display`	`%AttributeDisplay`	no	Display mode (default `"value"`)
`constant`	`%Bool`	no	Constant flag, only in device context (default `"no"`)
`align`	`%Align`	no	Text alignment (default `"bottom-left"`)

Display values: off, value, name, both

Coordinate System and Units

All Eagle coordinates are specified in millimeters as decimal values in the XML. Internally, the KiCad parser converts coordinates to nanometers for board context and to 100-nanometer units for schematic context using the ECOORD structure.

The Eagle coordinate system uses a standard Cartesian orientation with Y increasing upward. KiCad’s internal coordinate system has Y increasing downward, so the importer negates all Y-axis values during conversion:

KiCad_x =  Eagle_x
KiCad_y = -Eagle_y

Rotation Encoding

The %Rotation attribute type uses a string format: [S][M]R<degrees>

R prefix is always present, followed by the rotation angle in degrees
M prefix indicates mirroring
S prefix indicates the spin flag (text stays readable when rotated)

Examples: R0, R90, R180, R270, MR0 (mirrored, no rotation), SMR90 (spin
mirror + 90 degrees)

URN Format

Eagle uses URNs (Uniform Resource Names) to identify managed library assets:

urn:adsk.eagle:<ASSET_TYPE>:<ASSET_ID>[/<VERSION>]

ASSET_TYPE is one of: symbol, footprint, package, component, library
ASSET_ID is a numeric identifier
VERSION is optional

Example: urn:adsk.eagle:component:60986/2 references version 2 of component 60986.

Autodesk Fusion files may use an alternate URN format: urn:adsk.wipprod:fs.file:vf.RSKzNVZVQPeDNm7Bnfr3WQ

Special Text Variables

Eagle supports special text variables prefixed with >. The importer maps these to KiCad text variables:

Eagle Variable KiCad Variable

Eagle Variable	KiCad Variable
`>NAME`	`${REFERENCE}`
`>VALUE`	`${VALUE}`
`>PART`	`${REFERENCE}`
`>GATE`	`${UNIT}`
`>MODULE`	`${FOOTPRINT_NAME}`
`>SHEETNR`	`${#}`
`>SHEETS`	`${##}`
`>SHEET`	`${}/${#}`
`>SHEET_HEADLINE`	`${SHEETNAME}`
`>ASSEMBLY_VARIANT`	`${ASSEMBLY_VARIANT}`
`>DRAWING_NAME`	`${PROJECTNAME}`
`>LAST_DATE_TIME`	`${CURRENT_DATE}`
`>PLOT_DATE_TIME`	`${CURRENT_DATE}`

>NAME

${REFERENCE}

>VALUE

${VALUE}

>PART

${REFERENCE}

>GATE

${UNIT}

>MODULE

${FOOTPRINT_NAME}

>SHEETNR

${#}

>SHEETS

${##}

>SHEET

${}/${#}

>SHEET_HEADLINE

${SHEETNAME}

>ASSEMBLY_VARIANT

${ASSEMBLY_VARIANT}

>DRAWING_NAME

${PROJECTNAME}

>LAST_DATE_TIME

${CURRENT_DATE}

>PLOT_DATE_TIME

${CURRENT_DATE}

Text variables not in the table above are generically converted to ${VARIABLE_NAME}.

Eagle’s overbar notation uses ! as a toggle character. The importer converts this to KiCad’s ~ overbar notation.

Imported Elements

Schematic

Parts with library, device set, device, technology, and value resolution
Instances with gate placement, position, rotation, and smashed attributes
Multi-sheet and hierarchical design via sheets and modules
Nets and bus connectivity with segments, wires, junctions, and labels
Pin references and port references within net segments
Global attributes
Embedded library definitions (symbols, packages, device sets)
Text with font, alignment, and rotation
Circles, rectangles, polygons, and wires (including arcs via the curve attribute)
Special text variable mapping (>NAME to ${REFERENCE}, etc.)
Overbar notation conversion (! toggle to ~{} syntax)

Board

Component placements with position, rotation, mirroring, and locked/populate flags
Signal nets with routed wires, vias, polygon pours, and contact references
Net classes with default width, drill, and inter-class clearance rules
Design rules (pad elongation, mask expansion, paste shrink, pad annulus, via annulus, pad rounding, wire-to-wire spacing)
Through-hole pads with drill, diameter, shape, and rotation
SMD pads with size, roundness, layer, and rotation
Vias with drill, diameter, shape, layer extent, and solder mask forcing
Non-plated holes
Polygons with pour type, isolation, thermal, and orphan settings
Dimension annotations
Text and graphical elements on all layers

Library

Packages (footprints) with pads, SMDs, wires, text, circles, rectangles, holes, polygons, dimensions, and description
Symbols with pins, wires, text, circles, rectangles, polygons, and description
Device sets with gates, devices, connect pin-to-pad mappings, and technologies
Layer definitions with color, fill, visibility, and active state

Limitations

The <board> XML structure is traversed directly rather than parsed into the structured EDRAWING tree used for schematics and libraries.
The grouprefs attribute (IDREFS type) present on most graphical elements is not parsed.
3D package data (<package3d>, <package3dinstance>) is read but not used for 3D model import.
SPICE simulation data (<spice>, <pinmapping>, <model>) is parsed but not imported into KiCad’s simulation framework.
The <autorouter> section is ignored.
Design rule parameters beyond those listed in the design rules table are silently ignored.
The cap attribute on wires (flat vs round) is ignored; KiCad does not support flat line caps.
Variant-related elements (<variantdef>, <variant>) are parsed but variant-specific behavior is not implemented.
The <filter> element contents are parsed structurally but have no effect on import.

Eagle

Introduction

XML Document Structure

Element Tree Overview

Layer Definitions

Board Layer Number Table

Schematic Format (.sch)

Schematic Element Hierarchy

Part Element (<part>)

Instance Element (<instance>)

Gate Element (<gate>)

Device Set Element (<deviceset>)

Connect Element (<connect>)

Sheet Element (<sheet>)

Segment Element (<segment>)

Module Element (<module>)

Port Element (<port>)

Pin Direction Values

Board Format (.brd)

Board Element Hierarchy

Element (Component Placement)

Signal Element

Net Class Element (<class>)

Design Rules

Library Format (.lbr)

Library Element Hierarchy

Package Element

Symbol Element

Common Elements

Wire (<wire>)

Circle (<circle>)

Rectangle (<rectangle>)

Text (<text>)

Polygon (<polygon>)

Vertex (<vertex>)

Dimension (<dimension>)

Pin (<pin>)

Through-Hole Pad (<pad>)

SMD Pad (<smd>)

Via (<via>)

Hole (<hole>)

Attribute (<attribute>)

Coordinate System and Units

Rotation Encoding

URN Format

Special Text Variables

Imported Elements

Schematic

Board

Library

Limitations

Schematic Format (`.sch`)

Part Element (`<part>`)

Instance Element (`<instance>`)

Gate Element (`<gate>`)

Device Set Element (`<deviceset>`)

Connect Element (`<connect>`)

Sheet Element (`<sheet>`)

Segment Element (`<segment>`)

Module Element (`<module>`)

Port Element (`<port>`)

Board Format (`.brd`)

Net Class Element (`<class>`)

Library Format (`.lbr`)

Wire (`<wire>`)

Circle (`<circle>`)

Rectangle (`<rectangle>`)

Text (`<text>`)

Polygon (`<polygon>`)

Vertex (`<vertex>`)

Dimension (`<dimension>`)

Pin (`<pin>`)

Through-Hole Pad (`<pad>`)

SMD Pad (`<smd>`)

Via (`<via>`)

Hole (`<hole>`)

Attribute (`<attribute>`)