gEDA / Lepton EDA
Introduction
gEDA (GPL Electronic Design Automation) is an open-source EDA suite originally developed by Ales Hvezda beginning in 1998. Lepton EDA is a maintained fork of the gEDA/gaf (gschem and friends) toolsuite started in 2017. Both projects share compatible file formats and are licensed under the GNU General Public License v2 or later.
The gEDA/gaf suite consists of several tools with distinct file formats:
-
gschem / lepton-schematic produces schematic files (
.sch) and symbol files (.sym) in a simple line-oriented ASCII text format. -
pcb / lepton-pcb produces board layout files (
.pcb) and footprint files (.fp) in a parenthesized ASCII text format.
KiCad provides two separate importers for these formats:
| Extension | Content |
|---|---|
|
Schematic (gschem / lepton-schematic) |
|
Symbol definition (same format as schematic) |
|
Board layout (pcb / lepton-pcb) |
|
Footprint definition (same format as PCB Element) |
The schematic importer also processes .sym files internally to resolve
component references. The .sch extension is shared with KiCad’s own legacy
schematic format; the importer distinguishes gEDA files by checking for the
v YYYYMMDD version header on the first line.
|
Schematic Format (.sch / .sym)
gEDA schematics and symbol definitions use the same line-oriented ASCII text format.
The difference is context: .sch files describe full schematic sheets with component
placements and wiring, while .sym files describe individual symbol definitions with
pins and graphical shapes.
Version Line
Every file begins with a version line:
v YYYYMMDD N
YYYYMMDD is a release date (e.g., 20130925) that identifies the minimum gEDA version
required to read the file. N is the file format version number (typically 1 or 2).
The version number is optional in very early format files.
The KiCad importer validates that the date is a plausible value (>= 19700101) and uses it for version-aware parsing decisions.
Object Types
Each object begins with a single-character type identifier as the first non-whitespace character on a line. The parameters follow on the same line, separated by spaces.
| Type | Name | Description |
|---|---|---|
|
Component |
Places a symbol instance on the schematic |
|
Net |
Draws a net (wire) segment between two points |
|
Bus |
Draws a bus segment between two points |
|
Pin |
Defines a pin on a symbol |
|
Text |
Places text (also used for attributes inside |
|
Line |
Draws a graphical line segment |
|
Box |
Draws a rectangle |
|
Circle |
Draws a circle |
|
Arc |
Draws an arc |
|
Path |
Draws a complex path (SVG-like M/L/C/z commands) |
|
Picture |
Embeds a raster image |
|
Attributes |
Opens an attribute block (closed by |
|
Embedded |
Opens an inline embedded component definition (closed by |
Component (C line)
C x y selectable angle mirror basename.sym
| Field | Type | Description |
|---|---|---|
|
integer |
Origin position in mils |
|
integer |
1 if user-selectable, 0 if locked |
|
integer |
Rotation in degrees (0, 90, 180, 270) |
|
integer |
0 = normal, 1 = mirrored about Y axis |
|
string |
Symbol filename (e.g., |
Component lines are typically followed by an attribute block ({ }) containing
attribute text objects that override or extend the symbol’s default attributes.
Common attributes include:
| Attribute | Purpose |
|---|---|
|
Reference designator (e.g., |
|
Component value (e.g., |
|
Device type identifier |
|
PCB footprint name |
|
Sub-schematic filename for hierarchical designs |
|
Implicit net connection (format: |
|
Active slot number for multi-slot components |
|
Total number of slots |
|
Slot definition (format: |
|
Human-readable component description |
|
Symbol version string for compatibility tracking |
|
Set to |
Net (N line)
N x1 y1 x2 y2 color
Draws a net segment from (x1, y1) to (x2, y2). The color field is the gEDA
color index (typically 4 for nets). The importer ignores color and maps all nets to
KiCad wire objects.
Bus (U line)
U x1 y1 x2 y2 color ripperdir
Draws a bus segment. The ripperdir field (-1, 0, or 1) indicates which direction bus
entry stubs should extend. The importer creates KiCad bus wire objects and generates
bus entry objects where net endpoints touch bus segments.
Pin (P line)
P x1 y1 x2 y2 color pintype whichend
Defines a pin on a symbol. The first coordinate pair is the connection point (the end
that connects to nets) and the second is the other end. The whichend field (0 or 1)
specifies which endpoint is the active connection point.
Pin attributes are defined in a { } block following the P line:
| Attribute | Purpose |
|---|---|
|
Electrical pin number (maps to pad number in footprint) |
|
Pin sequence number (for SPICE netlisting) |
|
Human-readable pin name displayed on the symbol |
|
Electrical type (see Pin Electrical Types table) |
Pin Electrical Types
| gEDA Value | KiCad Mapping | Description |
|---|---|---|
|
|
Input pin |
|
|
Output pin |
|
|
Bidirectional |
|
|
Open collector |
|
|
Open emitter |
|
|
Passive |
|
|
Tri-state |
|
|
Power input (also used for power symbols) |
|
|
Not connected |
Text (T line)
T x y color size visibility show_name_value angle alignment num_lines text content line 1 text content line 2 ...
| Field | Type | Description |
|---|---|---|
|
integer |
Position in mils |
|
integer |
gEDA color index |
|
integer |
Text size in gEDA points (scaled to KiCad text height) |
|
integer |
0 = hidden, 1 = visible |
|
integer |
0 = show name and value, 1 = value only, 2 = name only |
|
integer |
Rotation in degrees (0, 90, 180, 270) |
|
integer |
Text alignment (0-8, maps to a 3x3 grid) |
|
integer |
Number of content lines following this header |
When a text object appears inside a { } block and contains an = character, it is
parsed as an attribute with a name=value pair. Floating text objects (outside attribute
blocks) are imported as KiCad SCH_TEXT objects.
Alignment Values
6 7 8 3 4 5 0 1 2
The alignment grid maps gEDA’s 0-8 values to horizontal and vertical justification. Value 0 is lower-left, 4 is middle-center, 8 is upper-right.
Overbar Notation
gEDA represents overbar text (a line drawn above characters) using _text\_ syntax.
The importer converts this to KiCad’s ~{text} notation. Escaped backslashes (\\)
become literal backslash characters.
Graphical Objects
Line (L)
L x1 y1 x2 y2 color linetype dashtype dashlength dashspace
Box (B)
B x y width height color linetype dashtype dashlength dashspace filltype fillwidth angle1 pitch1 angle2 pitch2
Circle (V)
V cx cy radius color linetype dashtype dashlength dashspace filltype fillwidth angle1 pitch1 angle2 pitch2
Arc (A)
A cx cy radius startangle sweepangle color linetype dashtype dashlength dashspace
Angles are in degrees. startangle is measured counter-clockwise from the positive
X axis. sweepangle is the angular extent of the arc.
Path (H)
H color linetype dashtype dashlength dashspace filltype fillwidth angle1 pitch1 angle2 pitch2 numlines M x,y L x,y C x1,y1 x2,y2 x3,y3 z
Paths use SVG-like drawing commands: M (move to), L (line to), C (cubic Bezier),
and z (close path).
Line Style Values
| Value | KiCad Mapping |
|---|---|
0 |
|
1 |
|
2 |
|
3 |
|
4 |
|
Fill Type Values
| Value | KiCad Mapping |
|---|---|
0 |
|
1 |
|
2 |
|
3 |
|
4 |
|
Attribute Blocks
Attribute blocks begin with { on its own line and end with } on its own line.
They can follow any object type but are most commonly found after C (component) and
P (pin) lines. Each entry inside the block is a T (text) object whose content
is a name=value pair.
C 40000 45000 1 0 0 resistor-1.sym
{
T 40300 45400 5 10 1 1 0 0 1
refdes=R1
T 40300 44700 5 10 1 1 0 0 1
value=10k
T 40300 44400 5 10 0 1 0 0 1
footprint=0805
}
Embedded Components
Components can be defined inline rather than loaded from external .sym files.
An embedded component begins with [ on its own line after the C line and its
attribute block, and ends with ]. The content between [ and ] is a complete
symbol definition using the same object types (P, L, B, V, A, T, H).
Symbol Discovery
When a C line references a symbol basename (e.g., resistor-1.sym), the symbol is
resolved through the following search order:
-
Check for an immediately following embedded
[ ]definition -
Search the built-in symbol library (common components embedded in the importer)
-
Scan gEDA system library directories
-
Parse
gafrcandgschemrcconfiguration files forcomponent-librarydirectives -
Generate a fallback rectangular symbol with the correct pin count
The built-in symbol library includes common passives (resistors, capacitors, inductors), semiconductors (diodes, LEDs, BJTs, MOSFETs), op-amps, logic gates (7400 series), power symbols (GND, Vcc, Vdd, etc.), and I/O port symbols.
Power Symbols
gEDA identifies power symbols by a net= attribute on the symbol definition (not on
the schematic instance). The format is net=NETNAME:PINNUMBER. Symbols with this
attribute become KiCad power symbols with a global label at the pin position.
Examples: net=GND:1, net=Vcc:1, net=+5V:1.
Hierarchical Schematics
gEDA supports hierarchical designs through the source= attribute on component instances.
A component with a source= attribute naming another .sch file becomes a KiCad
SCH_SHEET, and the sub-schematic is loaded recursively. The import call stack is
tracked to detect circular references.
Coordinate System and Units
Schematic Coordinates
gEDA schematic coordinates are integers in mils (thousandths of an inch) with the Y axis pointing upward. KiCad schematic coordinates use 100-nanometer internal units (IU) with the Y axis pointing downward.
Conversion formula:
kicad_iu = geda_mils * 254 kicad_y = (maxY - geda_y) * 254
The importer runs two passes: first it parses all objects and tracks the maximum Y coordinate, then it flips all Y coordinates during post-processing. This preserves relative positioning despite the axis inversion.
PCB Coordinates
The gEDA PCB format has three unit conventions determined by both file age and syntax:
| Delimiter | Era | Unit |
|---|---|---|
|
Pre-2008 |
1 mil (1000 units per inch) |
|
2008-2011 |
0.01 mil / centimil (100000 units per inch) |
|
2011+ |
Explicit unit suffix ( |
The bracket type after each keyword determines the unit convention. [ means centimils
(100000 per inch). Values with an explicit mm or mil suffix are converted to
centimils before further processing:
value_in_mm: centimils = value * 100000 / 25.4 value_in_mil: centimils = value * 100
All values are then converted to KiCad internal units (nanometers):
kicad_nm = centimils * 0.01 * IU_PER_MILS
PCB Format (.pcb)
The gEDA PCB format is an ASCII text format using parenthesized or bracketed syntax.
Each object is a keyword followed by parameters enclosed in [ ] (new format) or
( ) (old format).
File Header
A PCB file begins with an optional comment block (lines starting with #), a file
version declaration, and a board header:
# release: pcb 20140316
FileVersion[20091103]
PCB["board_name" board_width board_height]
The PCB header declares the board name and dimensions. It is followed by global
settings:
Grid[1000.000000 0.0000 0.0000 0]
PolyArea[3100.006200]
Thermal[0.500000]
DRC[10.00mil 10.00mil 10.00mil 10.00mil 15.00mil 10.00mil]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,10.00mil,36.00mil,20.00mil,10.00mil:Power,25.00mil,..."]
Element (Component / Footprint)
Elements define footprints placed on the board. Multiple syntax variants exist depending on format version:
Element [SFlags "Desc" "Name" "Value" MX MY TX TY TDir TScale TSFlags]
Element (NFlags "Desc" "Name" "Value" MX MY TX TY TDir TScale TNFlags)
Element (NFlags "Desc" "Name" "Value" TX TY TDir TScale TNFlags)
Element (NFlags "Desc" "Name" TX TY TDir TScale TNFlags)
Element ("Desc" "Name" TX TY TDir TScale TNFlags)
| Field | Type | Description |
|---|---|---|
|
string |
Symbolic flags (e.g., |
|
hex |
Numeric flags as hexadecimal |
|
string |
Footprint description |
|
string |
Reference designator |
|
string |
Component value |
|
integer |
Absolute mark position (board coordinates) |
|
integer |
Text offset relative to mark |
|
integer |
Text direction (0-3, in 90-degree increments) |
|
integer |
Text size scaling factor |
An Element contains sub-objects enclosed between ( and ):
-
Pin— through-hole pad -
Pad— surface-mount pad -
ElementLine— silkscreen line -
ElementArc— silkscreen arc -
Attribute("name" "value")— component attribute
Pin (Through-Hole Pad)
Pin [rX rY Thickness Clearance Mask Drill "Name" "Number" SFlags] Pin (rX rY Thickness Clearance Mask Drill "Name" "Number" NFlags) Pin (aX aY Thickness Drill "Name" "Number" NFlags) Pin (aX aY Thickness Drill "Name" NFlags) Pin (aX aY Thickness "Name" NFlags)
| Field | Type | Description |
|---|---|---|
|
integer |
Position relative to Element mark |
|
integer |
Copper annular ring outer diameter |
|
integer |
Polygon clearance (total gap, both sides combined) |
|
integer |
Solder mask opening diameter |
|
integer |
Drill hole diameter |
|
string |
Pin name (arbitrary; assigned by netlist on instantiation) |
|
string |
Pin number (maps to KiCad pad number for electrical connectivity) |
|
string |
Symbolic flags |
gEDA specifies clearance as the total gap on both sides of the pad.
The importer halves this value for KiCad, which defines clearance as
the gap on one side.
Similarly, the mask value represents the solder mask opening diameter
rather than a margin. The importer converts it:
kicad_mask_margin = (mask_diameter - pad_diameter) / 2.
|
Pad (Surface-Mount Pad)
Pad [rX1 rY1 rX2 rY2 Thickness Clearance Mask "Name" "Number" SFlags] Pad (rX1 rY1 rX2 rY2 Thickness Clearance Mask "Name" "Number" NFlags) Pad (aX1 aY1 aX2 aY2 Thickness "Name" "Number" NFlags) Pad (aX1 aY1 aX2 aY2 Thickness "Name" NFlags)
A Pad is defined by a line segment from (X1,Y1) to (X2,Y2) with a given thickness. The resulting pad shape is the line segment swept by a circle (or square) of the specified thickness.
The pad shape depends on the square flag:
| Flag | Shape |
|---|---|
Not set |
Oval if the two endpoints differ; Circle if they coincide |
|
Rectangle |
The onsolder flag (bit 0x0080) places the pad on the back copper layer instead of the
front.
ElementLine and ElementArc
ElementLine [X1 Y1 X2 Y2 Thickness] ElementArc [X Y Width Height StartAngle DeltaAngle Thickness]
These define silkscreen graphics within an Element. ElementLine draws a simple line
segment. ElementArc draws an arc (or circle when DeltaAngle is 360 degrees).
gEDA PCB does not directly support circles as a primitive. Full circles are represented
as arcs with a DeltaAngle of 360.
Arc angles use gEDA’s convention:
-
Angles are in degrees, measured counter-clockwise from the 3 o’clock position
-
The importer adds 180 degrees to the start angle and negates the delta angle to convert to KiCad’s angle convention
-
Width and Height are averaged to produce a radius, since KiCad does not support elliptical arcs
Via
Via [X Y Thickness Clearance Mask Drill "Name" SFlags]
All vias are imported as through-hole vias spanning all copper layers (F.Cu to B.Cu). The gEDA format does not support blind or buried vias.
Layer
Layer(N "name")
(
Line[X1 Y1 X2 Y2 Thickness Clearance SFlags]
Arc[X Y Width Height Thickness Clearance StartAngle DeltaAngle SFlags]
Polygon(SFlags) ( [X Y] [X Y] ... )
)
Layer blocks contain the board-level copper traces, shapes, arcs, and copper polygons. Layer numbering is 1-based:
-
Layer 1 is the component (top) side
-
Layer 2 is the solder (bottom) side
-
Layers 3 through 16 are inner copper layers
Lines on copper layers are imported as PCB_TRACK objects. Lines on non-copper layers
become PCB_SHAPE objects. Arcs on copper layers become PCB_ARC objects. Polygons
become ZONE objects.
NetList
NetList()
(
Net("netname" "style")
(
Connect("refdes-padnumber")
)
)
The NetList block at the end of the file defines the electrical connectivity.
Each Net contains Connect entries that reference component pads using the
format refdes-padnumber (e.g., R1-1, C1-2).
Flags
gEDA PCB objects use two flag formats:
| Format | Example |
|---|---|
Numeric |
|
Symbolic |
|
Key flag values:
| Bit Mask | Name | Description |
|---|---|---|
0x0080 |
|
Element or pad is on the solder (bottom) side |
0x0100 |
|
Pin or pad has a square shape |
Layer Mapping
PCB Layer Mapping
Layer mapping uses both the numeric index and the layer name string. Name-based matching takes precedence when the name contains a recognized keyword.
| gEDA Layer | Typical Name | KiCad Layer | Match Rule |
|---|---|---|---|
1 |
|
|
Name contains "component" or "top", or layer 1 without "solder" |
2 |
|
|
Name contains "solder" or "bottom", or layer 2 |
3-16 |
|
|
Inner copper by index (layer - 3) |
any |
|
|
Name contains "silk" (front by default) |
any |
|
|
Name contains "silk" and "solder" or "bottom" |
any |
|
|
Name contains "outline" or "route" |
any |
|
|
Name contains "mask" (front by default) |
any |
|
|
Name contains "mask" and "solder" or "bottom" |
any |
|
|
Name contains "paste" (front by default) |
any |
|
|
Name contains "paste" and "solder" or "bottom" |
any |
|
|
Name contains "fab" |
Footprint Library Format
gEDA PCB footprint libraries are directories containing individual .fp files. Each
.fp file holds a single Element definition using the same syntax as elements in
.pcb board files.
Footprints are loaded from standalone .fp files or from Element blocks embedded in
.pcb board files. Footprint names come from the .fp filename without extension.
Imported Elements
Schematic
-
Component instances with position, rotation, and mirroring
-
Symbol graphics (lines, boxes, circles, arcs, paths) from
.symfiles -
Pins with electrical type, number, name, and sequence
-
Net wire segments with automatic junction placement at 3+ endpoint intersections
-
Bus segments with bus entry generation
-
Text objects (both floating and attribute-bound)
-
Hierarchical sub-schematics via
source=attribute (recursive, with loop detection) -
Power symbols identified by
net=attribute (converted to KiCad power symbols) -
Multi-slot component support via
numslots/slot/slotdefattributes -
Embedded inline component definitions (via
[ ]blocks) -
Overbar notation (
_text\_converted to~{text}) -
Reference images (G picture objects)
-
Common symbols from built-in library (resistors, capacitors, diodes, transistors, logic gates, power symbols, op-amps, and I/O ports)
-
Attribute visibility and show-name-value settings
-
Page sizing with automatic enlargement and centering to fit content
PCB
-
Board dimensions from
PCBheader -
Component footprints with position, reference designator, value, and description
-
Through-hole pins (circle or square shapes, with drill size)
-
Surface-mount pads (rectangle, oval, or circle shapes, front or back layer)
-
Pad clearance and solder mask margin (converted from gEDA’s full-gap and diameter conventions to KiCad’s per-side margin conventions)
-
Through-hole vias (full-stack only)
-
Copper traces on all layers (imported as
PCB_TRACKobjects) -
Copper arcs on all layers (imported as
PCB_ARCobjects) -
Copper polygons (imported as
ZONEobjects) -
Graphical lines and arcs on non-copper layers
-
Silkscreen lines and arcs within footprints (
ElementLine,ElementArc) -
Multi-layer copper configurations (up to 16 layers)
-
Net connectivity from
NetListblock -
Bottom-side component placement via
onsolderflag -
Net-based pad assignment from the netlist section
Footprint Libraries
-
Individual
.fpfiles from directory-based libraries -
Element definitions with description, reference, and value fields
-
Pin and Pad objects with all shape and clearance parameters
-
Silkscreen graphics (ElementLine and ElementArc)
-
Component attributes
Limitations
-
The PCB importer only supports through-hole vias. Blind and buried vias are not part of the gEDA PCB format.
-
Elliptical arcs in the PCB format are approximated as circular arcs by averaging the width and height radii.
-
The schematic importer does not support multi-page schematics within a single file. gEDA stores each page as a separate
.schfile. -
gEDA’s
colorfield on all objects is ignored during import. KiCad uses its own color scheme. -
The
graphical=1attribute marks symbols as non-electrical, but some graphical symbols (like title blocks) may not be positioned correctly after coordinate transformation. -
Symbol slot definitions (
slotdef=) with complex pin remapping may not map correctly to KiCad’s multi-unit symbol model in all cases. -
The PCB format’s
Stylesdefinition (routing styles with default trace width, via size, and clearance) is not imported. -
The
Groupsdefinition (layer grouping for the PCB editor) has no KiCad equivalent and is ignored. -
Bus naming conventions differ between gEDA and KiCad. gEDA uses a flat bus model while KiCad uses named bus syntax (
BUS{signal1 signal2 …}). -
Fill patterns (hatch angle and pitch) from schematic graphical objects are simplified during import.
-
DRC rules from the PCB
DRCline are not imported into KiCad’s design rule system.
Undocumented and Partially Understood Areas
-
pinseqordering for SPICE netlisting is mapped to KiCad’s pin sequence, but the importer does not replicate gEDA’s SPICE export conventions. -
symversionis read but not acted on. gEDA uses it to detect outdated symbol instantiations in schematics. -
model-nameattributes on components (3D and simulation model references) are not processed. -
component-library-commandandcomponent-library-funcsRC file directives (which run external programs to generate symbol libraries dynamically) are not supported. -
The
Thermalvalue from the PCB header (thermal relief scaling factor) is parsed but not applied to imported zones. -
Polygon hole support in the PCB format (nested polygon cutouts) is untested.
-
The
PolyAreasetting (minimum polygon area threshold) is ignored. -
Picture objects (G) may lose resolution or aspect ratio during import.